gem5 - gem5

Age	Commit message (Expand)	Author
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-16	Config: Fix a typo in the se.py script for setting fastmem	Andreas Hansson
2012-05-03	Config: Fix help msg for option --mem-size	Jayneel Gandhi
2012-04-17	SE Config: Changed se.py to support multithreaded mode	Jayneel Gandhi
2012-04-16	Config: Add command line options for disk image and memory size	Jayneel Gandhi
2012-04-06	ruby: set SimpleTiming as the default cpu	Brad Beckmann
2012-04-06	rubytest: seperated read and write ports.	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-04-05	Ruby: Fix the example configurations option parsing	Andreas Hansson
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-27	Config: Move setWorkCountOptions() to Simulation.py	Nilay Vaish
2012-03-16	ruby_fs.py: Add call to createInterruptController()	Nilay Vaish
2012-03-16	FSConfig.py: fix a typo makeLinuxAlphaRubySystem	Nilay Vaish
2012-03-11	se.py: Changes to ruby portion due to SE/FS merge	Nilay Vaish
2012-03-09	ARM: Fix memory starting at non-zero address and exceeding max mem for a system.	Ali Saidi
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-03-01	Config: make option ruby available always	Nilay Vaish
2012-02-26	Make the IO bridge accept address headed to all the local APICs.	Gabe Black
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	configs: fix minor config bugs posted on the mailing list	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-02-05	X86: Rename the bridge which allows commnication back to the local APICs.	Gabe Black
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-28	Config: Enable O3 CPU and Ruby in FS mode	Nilay Vaish
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-26	configs: actually add ARMv7a-like cpu/cache file	Ronald Dreslinski
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski
2012-01-25	MEM: Fix fs.py by specifying the range size rather than end	Andreas Hansson
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-11	Ruby: Use map option for selecting b/w sparse and memory vector	Nilay Vaish
2012-01-11	Config: Add support for restoring using a timing CPU	Nilay Vaish
2012-01-10	Ruby: remove the files related to the tracer	Nilay Vaish
2012-01-10	Config: Remove short option string for cpu type	Nilay Vaish