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AgeCommit message (Expand)Author
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-11Ruby: Use map option for selecting b/w sparse and memory vectorNilay Vaish
2012-01-11Config: Add support for restoring using a timing CPUNilay Vaish
2012-01-10Ruby: remove the files related to the tracerNilay Vaish
2012-01-10Config: Remove short option string for cpu typeNilay Vaish
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-09cpu2000: Add missing art benchmark to allAli Saidi
2012-01-07Ruby Cache: Add param for marking caches as instruction onlyNilay Vaish
2012-01-05Config: Add an option of type 'choice' for cpu typeNilay Vaish
2011-12-15ARM: Update config files for Android/BBench images available on website.Anthony Gutierrez
2011-12-01config: command line option to specify ruby output filegloh
2011-12-01VNC: Add support for capturing frame buffer to file each time it is changed.Chris Emmons
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-11-04GARNET: adding a fault model for resilient on-chip network research.Tushar Krishna
2011-10-29Ruby FS: Add the options for kernel and simulation scriptNilay Vaish
2011-10-19ARM: Fix small bug in config script that prevents android from bootingAli Saidi
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-08-02Scons: Drop RUBY as compile time option.Nilay Vaish
2011-07-26Ruby: Fix instantiations of DMA controller and sequencerNilay Vaish
2011-07-25Ruby: Fix dma controller configs/ruby/MI_example.pyNilay Vaish
2011-07-11se.py: Fixes the way ruby's options are addedNilay Vaish
2011-07-03Network_test: Conform it with functional access changes in RubyNilay Vaish
2011-06-30config: removed unnecessary slashesBrad Beckmann
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-21configs: remove -p from ruby_network_test.pyTushar Krishna
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
2011-05-07NetworkTest: added sim_cycles parameter to the network tester.Tushar Krishna
2011-05-04ARM: Configure bootloader parametersAli Saidi
2011-04-28network: basic link bw for garnet and simple networksBrad Beckmann
2011-04-28network: convert links & switches to first class C++ SimObjectsBrad Beckmann
2011-04-20python: fix another bug from changes to main.pyNathan Binkert
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-28Config: Import math in MI_example.pyNilay Vaish
2011-03-25ruby: fixed cache index settingBrad Beckmann
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
2011-03-19configs: combine ruby_se.py and se.py to avoid all that code duplicationLisa Hsu
2011-03-19enable x86 workloads on se.pyLisa Hsu
2011-03-19se.py: Modify script to make multiprogramming much easier.Lisa Hsu
2011-03-17ARM: Bare metal system should have 256MB of RAM.Ali Saidi