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2019-10-29mem: Fix DRAM controller to operate on its own address spaceNikos Nikoleris
Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28configs: Update HPI to use ArmDTB and ArmITB.Gabe Black
Change-Id: I67693e9d79e89f151e30c585ad565deac53c77c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22203 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-28configs: Fix undefined BaseCPUDaniel R. Carvalho
When using NULL ISA BaseCPU is undefined, and therefore the isinstance call generates a NameError. Change-Id: Ia4582606b775cdb20829966f8e312a333a55b6f3 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21959 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-22configs: Clean setupBootLoader signatureGiacomo Travaglini
This is because the bus parameter is not used anymore Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-22configs: Do not assume bootmem is a System childGiacomo Travaglini
As far as I can see bootmem is used in Arm systems only. With https://gem5-review.googlesource.com/c/public/gem5/+/21604 bootmem has been moved from system to system.realview. This patch fix things by removing the assumption that the bootmem SimObject lives under the system. It is now trying to getattr a reference of the bootmem. It is the ISA specific system builder's duty to bind the bootmem reference (_bootmem) to the real bootmem object Change-Id: I1e7405b5cb186de13c44bfd93fb4c8a1a5447f24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22001 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-22dev-arm, configs: Using _on_chip_memory for on chip memoryGiacomo Travaglini
This patch is pulling the on-chip memory outside of the on_chip_devices list. The external interface will be more or less the same: configuration scripts will still use the attachOnChipIO method; a new kw argument has been added in order to store mem_ports. We want to provide to on-chip memory the same mechanism used when collecting on-chip dma ports. This is needed when using Ruby, since we need to pass a non None mem_ports to prevent the bootmem to be wired to the bus. Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-15configs: Add simpleSystem helper to generate devices.SimpleSystemGiacomo Travaglini
This patch will make it possible to generate a SimpleSystem inheriting from a configurable base class. More practically it will be possible to inherit from a baremetal System (ArmSystem) rather than from a LinuxArmSystem Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-11mem-ruby: Allow Ruby to use all replacement policies in ClassicJingQuJQ
Add support in Ruby to use all replacement policies in Classic. Furthermore, if new replacement policies are added to the Classic system, the Ruby system will recognize new policies without any other changes in Ruby system. The following list all the major changes: * Make Ruby cache entries (AbstractCacheEntry) inherit from Classic cache entries (ReplaceableEntry). By doing this, replacement policies can use cache entries from Ruby caches. AccessPermission and print function are moved from AbstractEntry to AbstractCacheEntry, so AbstractEntry is no longer needed. * DirectoryMemory and all SLICC files are changed to use AbstractCacheEntry as their cache entry interface. So do the python files in mem/slicc/ast which check the entry interface. * "main='false'" argument is added to the protocol files where the DirectoryEntry is defined. This change helps differentiate DirectoryEntry from CacheEntry because they are both the instances of AbstractCacheEntry now. * Use BaseReplacementPolicy in Ruby caches instead of AbstractReplacementPolicy so that Ruby caches will recognize the replacement policies from Classic. * Add getLastAccess() and useOccupancy() function to Classic system so that Ruby caches can use them. Move lastTouchTick to ReplacementData struct because it's needed by getLastAccess() to return the correct value. * Add a 2-dimensional array of ReplacementData in Ruby caches to store information for different replacement policies. Note that, unlike Classic caches, where policy information is stored in cache entries, the policy information needs to be stored in a new 2-dimensional array. This is due to Ruby caches deleting the cache entry every time the corresponding cache line get evicted. Change-Id: Idff6fdd2102a552c103e9d5f31f779aae052943f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20879 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-10dev-arm, configs: Remove RealViewPBX platformGiacomo Travaglini
This is an old unused platform. We should support VExpress_GEM5 based platforms only. Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07configs: Isolate ISA related object listsDaniel R. Carvalho
Some objects are not compiled when using NULL ISA, and therefore their object lists cannot exist. Change-Id: I93ec576229916c892de50bb6c73cd602e18a3654 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21439 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07config: skip access to branchPred in ARM KVMCiro Santilli
Prevents runtime error: AttributeError: object 'ArmV8KvmCPU' has no attribute 'branchPred' Change-Id: Ic5765fd560381cbacc2fa2fd2e6f79d98433c535 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21299 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01configs: Port PlatformConfig to the common object listDaniel R. Carvalho
Port PlatformConfig to use the common object list. Change-Id: If62e596bf1f28b49994da3a2800450d163383755 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port MemConfig to the common object listDaniel R. Carvalho
Port MemConfig to use the common object list. Change-Id: If421c2745ac3431718a5170314045b456fc64a90 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port HWPConfig to the common object listDaniel R. Carvalho
Port HWPConfig to use the common object list. Change-Id: I86db6b872808f754193dbf5814dd6c951c8f1980 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20591 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port BPConfig to use the common object listDaniel R. Carvalho
Port BPConfig to use the common object list. Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Port CPUConfig to use the common object listDaniel R. Carvalho
Factor out ObjectList functionality from CPUConfig. Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Create a basic ObjectListDaniel R. Carvalho
There are multiple files that reimplement the same functionality of listing and getting available modules for class instantiation. Create a base class that can be derived and reduce code duplication. Change-Id: I96bf47b1ffd10893691b0b95591969b38894dd65 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20588 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30configs: Remove is_atomic_cpu checkDaniel R. Carvalho
Commit 224f2d50a9873d054f486d7661d947db76f4cf68 removed all instances of is_atomic_cpu. Change-Id: I1101fbdbc16dc5d093ab87d3817308176559a548 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20659 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-09-30cpu: Make use of DRAMCtrl::AddrMap in the traffic generatorsNikos Nikoleris
Use the enum defined in the memory controller rather than custom strings and int that are later converted to the DRAMCtrl::AddrMap enum. Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-03configs: Fix replacement policy assignmentDaniel R. Carvalho
Commit d207e9ccee411877fdeac80bb68a27900560f50f reworked the tags to split the replacement policies, however the name of the variable that contains the replacement policy changed between patch revisions, which was not updated accordingly in the configs files. Change-Id: I2072529e2c7d54197c371bcaa323bfd9f34ec3ba Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20548 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21configs: root, platform options in fs bigLITTLEAdrian Herrera
(1) Two new options are added to fs_bigLITTLE.py: - "root": disk/partition containing the rootfs (def. "/dev/vda1") - "machine-type": hardware platform class (def. "VExpress_GEM5_V1") + Accepts platform classes from PlatformConfig (2) Default kernel is not available in public uploads, force the user to provide its own kernel instead of crashing. Change-Id: I88283ae12cd7289e15b9277ea2cc382e9136f11c Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20148 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-30configs, arch-arm: Check if gic has cpu_addr attributeChun-Chen TK Hsu
Add this check because Gicv3 does not have the cpu_addr attribute. Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the following command to boot Debian. M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \ --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \ --kernel $PWD/fs_files/binaries/vmlinux \ --disk $PWD/fs_files/disks/disk.img \ --cpu-type atomic --big-cpus 1 --little-cpus 0 Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-20configs: Fix NULL dram-lowp regressionsGiacomo Travaglini
The problem arises since there are some scripts (like NULL dram regressions) which are making use of MemConfig.py without using Opions.py so they won't have the new enable-dram-powerdown option Change-Id: Id9769cce2e8a25b57da76f07eeebd279a6e00440 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19268 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10configs: Fix read_config to work with new AddrRange serializationNikos Nikoleris
Change-Id: I122c77c34c2f8c75f8b32682be858f651112ce89 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19151 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10configs: Add python3 workarounds in read_configNikos Nikoleris
Change-Id: Ib065f41b87e5ada9535b9c2645067162aa69234b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19150 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-06mem: Option to toggle DRAM low-power statesMatthew Poremba
Adding an option to enable DRAM low-power states. The low power states can have a significant impact on application performance (sim_ticks) on the order of 2-3x, especially for compute-gpu apps. The options allows for it to easily be enabled/disabled to compare performance numbers. The option is disabled by default. Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548 Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31config, arm: memoryMode testWilly Wolff
Commit 9a13acaa367769c38859342de9bc35aac59a6710 doesn't comply with the same behaviour. The conditional test the memory mode on the same cluster, while it should test the other cluster. Change-Id: If3a7863f0905e66a548001d8e74689f5dd07179c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17748 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-17configs: Generalize FileSystemConfig for non se.pyJason Lowe-Power
This patch updates the FileSystemConfig so it works with more kinds of config scripts (e.g., the Learning gem5 scripts). There are 4 main changes: - Added system as a parameter to the config_filesystem function so the function can search the system for the number of CPUs instead of relying on options from Options.py - Instead of calling redirect_paths everywhere config_filesystem is used, now it is implicitly called. - Cleaned up the Ruby scripts a bit to remove redundant calls to config_filesystem - Added a config_filesystem call to the Ruby Learning gem5 script (currently the only Learning gem5 script that requires it). In the future, I think it would be better to move the config_filesystem call into simulate.py, probably into the instantiate function. I tried to use the per-CPU configuration parameters instead of options from Options.py, but that's not possible until after the SimObject params have been finalized in instantiate. Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14mem-ruby: Cache latencies for MOESI_CMP_dirTiago Muck
Modified both L1 and L2 controllers to take into account the cache latency parameters. Default values in the configuration script updated as well. Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Hit latencies defined by the controllersTiago Muck
Removed the icache/dcache hit latency parameters from the Sequencer. They were replaced by the mandatory queue enqueue latency that is now defined by the top-level cache controller. By default, the latency is defined by the mandatory_queue_latency parameter. When the latency depends on specific protocol states or on the request type, the protocol may override the mandatoryQueueLatency function. Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Change MOESI_CMP_Dir L2 addressingTiago Muck
L1 controller selects the L2 to message based on the assigned address ranges instead of explicitly interleaving bits in the L1 controller. This simplifies the L1 controller implementation a bit and allows for more flexibility when changing the address->controller mapping. Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14configs: Fix duplicate branchPred reference in Simulation.pyJavier Bueno
Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18769 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-13config: add an option to list and select indirect branch predictorJairo Balart
Change-Id: I9a855d36de7d95b7785ff8a897899037cea6a3d8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-10config, sim-se: bugfix for 54c77aa0Brandon Potter
The NULL ISA does not have some members for the options class which are referenced by the FileSystemConfig code. Create default values for the members so that the simulation does not fail during the configuration phase. Change-Id: Ie65bf0e5550c964eae42d1df4c36c2c5bc4ea703 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18748 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-09configs: Fix FileSystemConfig importDaniel R. Carvalho
Add source to FileSystemConfig import Change-Id: I2cd70a332244cbdc58b1b7c06d589b4339f6e19a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18709 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-04-25configs: faux-filesystem fix w/ ruby in se modeDavid Hashe
These changes are needed so that the config scripts can report cache hierarchy information to the faux filesystem. This is useful for the ROCm runtime when it reads psuedofiles from the host filesytem from "/proc". Change-Id: Iad3e6c088d47c9b93979f584de748367eae8259b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12121 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25sim-se: add a faux-filesystemDavid Hashe
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24config: Add flag options to set the hardware prefetchers to useJavier Bueno
This patch adds three flag options to set the prefetcher class of the L1i cache, L1d cache and L2 cache. Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17709 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-22configs: Use param to get number of processorsPo-Hao Su
Although the parameter np is the same as options.num_cpus. But we should get the number of processors from the parameters of the function. Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-08learning_gem5,configs: Update ruby_testJason Lowe-Power
Use SimpleMemory instead of DDR3 so we can use the timing results in tests. By using SimpleMemory, even if the DRAM timing changes the timing of this test won't change. I expect the timing of SimpleMemory to never change. Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Fix import path error in learning_gem5 part3Jason Lowe-Power
Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Add full path for learning_gem5 binariesJason Lowe-Power
Change-Id: Ie48429d65e322136109a223ed404937989aae494 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Removed redudant exec-style importRyan Gambord
garnet_synth_traffic.py imports common.Options on line 40, so exec'ing the Options.py file again seems redundant. It also runs Options.py as a script rather than a module, which throws ValueError: Attempted relative import in non-package due to the recent change to python3 imports. Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27config: Use the corresponding HPI Caches when using the HPI cpuJavier Bueno
The HPI cpu comes with specific cache definitions, but they are ignored when using this cpu. This patch solves this in the same way it is done for the O3_ARM_v7a cpu. Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26configs: fix class reference in CacheConfigsJavier Bueno
One reference was not properly updated when changing to absolute import paths Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-25configs: Remove default kernel value from system creationDaniel R. Carvalho
Kernel was being set using a placeholder and then assigned the correct value. This would generate the following error if the placeholder file did not exist: 'IOError: Can't find file <placeholder> on path' This patch follows the same directions of commit 12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default values, forcing the user to properly configure the kernel. Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-18configs: Use absolute import pathsAndreas Sandberg
Use absoluate import paths to be Python 3 compatible. This also imports absolute_import from __future__ to ensure that Python 2.7 behaves the same way as Python 3. Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-26configs: Fix Python 3 iterator and exec compatibility issuesAndreas Sandberg
Python 2.7 used to return lists for operations such as map and range, this has changed in Python 3. To make the configs Python 3 compliant, add explicit conversions from iterators to lists where needed, replace xrange with range, and fix changes to exec syntax. This change doesn't fix import paths since that might require us to restructure the configs slightly. Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16002 Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-25systemc: Update the sc_main.py config to use m5.systemc.Gabe Black
Change-Id: I386970b5cf7ee1262b259abfb3b5e902ccea9991 Reviewed-on: https://gem5-review.googlesource.com/c/16568 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13configs: simpoint-profile usable with NonCachingCPUs onlyGiacomo Travaglini
NonCachingCPU is replacing the Atomic+fastmem option. Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15935 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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