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2019-05-17configs: Generalize FileSystemConfig for non se.pyJason Lowe-Power
This patch updates the FileSystemConfig so it works with more kinds of config scripts (e.g., the Learning gem5 scripts). There are 4 main changes: - Added system as a parameter to the config_filesystem function so the function can search the system for the number of CPUs instead of relying on options from Options.py - Instead of calling redirect_paths everywhere config_filesystem is used, now it is implicitly called. - Cleaned up the Ruby scripts a bit to remove redundant calls to config_filesystem - Added a config_filesystem call to the Ruby Learning gem5 script (currently the only Learning gem5 script that requires it). In the future, I think it would be better to move the config_filesystem call into simulate.py, probably into the instantiate function. I tried to use the per-CPU configuration parameters instead of options from Options.py, but that's not possible until after the SimObject params have been finalized in instantiate. Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14mem-ruby: Cache latencies for MOESI_CMP_dirTiago Muck
Modified both L1 and L2 controllers to take into account the cache latency parameters. Default values in the configuration script updated as well. Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Hit latencies defined by the controllersTiago Muck
Removed the icache/dcache hit latency parameters from the Sequencer. They were replaced by the mandatory queue enqueue latency that is now defined by the top-level cache controller. By default, the latency is defined by the mandatory_queue_latency parameter. When the latency depends on specific protocol states or on the request type, the protocol may override the mandatoryQueueLatency function. Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Change MOESI_CMP_Dir L2 addressingTiago Muck
L1 controller selects the L2 to message based on the assigned address ranges instead of explicitly interleaving bits in the L1 controller. This simplifies the L1 controller implementation a bit and allows for more flexibility when changing the address->controller mapping. Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14configs: Fix duplicate branchPred reference in Simulation.pyJavier Bueno
Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18769 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-13config: add an option to list and select indirect branch predictorJairo Balart
Change-Id: I9a855d36de7d95b7785ff8a897899037cea6a3d8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-10config, sim-se: bugfix for 54c77aa0Brandon Potter
The NULL ISA does not have some members for the options class which are referenced by the FileSystemConfig code. Create default values for the members so that the simulation does not fail during the configuration phase. Change-Id: Ie65bf0e5550c964eae42d1df4c36c2c5bc4ea703 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18748 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-09configs: Fix FileSystemConfig importDaniel R. Carvalho
Add source to FileSystemConfig import Change-Id: I2cd70a332244cbdc58b1b7c06d589b4339f6e19a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18709 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-04-25configs: faux-filesystem fix w/ ruby in se modeDavid Hashe
These changes are needed so that the config scripts can report cache hierarchy information to the faux filesystem. This is useful for the ROCm runtime when it reads psuedofiles from the host filesytem from "/proc". Change-Id: Iad3e6c088d47c9b93979f584de748367eae8259b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12121 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25sim-se: add a faux-filesystemDavid Hashe
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24config: Add flag options to set the hardware prefetchers to useJavier Bueno
This patch adds three flag options to set the prefetcher class of the L1i cache, L1d cache and L2 cache. Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17709 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-22configs: Use param to get number of processorsPo-Hao Su
Although the parameter np is the same as options.num_cpus. But we should get the number of processors from the parameters of the function. Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-08learning_gem5,configs: Update ruby_testJason Lowe-Power
Use SimpleMemory instead of DDR3 so we can use the timing results in tests. By using SimpleMemory, even if the DRAM timing changes the timing of this test won't change. I expect the timing of SimpleMemory to never change. Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Fix import path error in learning_gem5 part3Jason Lowe-Power
Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Add full path for learning_gem5 binariesJason Lowe-Power
Change-Id: Ie48429d65e322136109a223ed404937989aae494 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Removed redudant exec-style importRyan Gambord
garnet_synth_traffic.py imports common.Options on line 40, so exec'ing the Options.py file again seems redundant. It also runs Options.py as a script rather than a module, which throws ValueError: Attempted relative import in non-package due to the recent change to python3 imports. Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27config: Use the corresponding HPI Caches when using the HPI cpuJavier Bueno
The HPI cpu comes with specific cache definitions, but they are ignored when using this cpu. This patch solves this in the same way it is done for the O3_ARM_v7a cpu. Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26configs: fix class reference in CacheConfigsJavier Bueno
One reference was not properly updated when changing to absolute import paths Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-25configs: Remove default kernel value from system creationDaniel R. Carvalho
Kernel was being set using a placeholder and then assigned the correct value. This would generate the following error if the placeholder file did not exist: 'IOError: Can't find file <placeholder> on path' This patch follows the same directions of commit 12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default values, forcing the user to properly configure the kernel. Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-18configs: Use absolute import pathsAndreas Sandberg
Use absoluate import paths to be Python 3 compatible. This also imports absolute_import from __future__ to ensure that Python 2.7 behaves the same way as Python 3. Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-26configs: Fix Python 3 iterator and exec compatibility issuesAndreas Sandberg
Python 2.7 used to return lists for operations such as map and range, this has changed in Python 3. To make the configs Python 3 compliant, add explicit conversions from iterators to lists where needed, replace xrange with range, and fix changes to exec syntax. This change doesn't fix import paths since that might require us to restructure the configs slightly. Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16002 Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-25systemc: Update the sc_main.py config to use m5.systemc.Gabe Black
Change-Id: I386970b5cf7ee1262b259abfb3b5e902ccea9991 Reviewed-on: https://gem5-review.googlesource.com/c/16568 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13configs: simpoint-profile usable with NonCachingCPUs onlyGiacomo Travaglini
NonCachingCPU is replacing the Atomic+fastmem option. Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15935 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12systemc: config: Don't inject a custom argv[0] in sc_main.py.Gabe Black
argv[0] is already part of sys.argv, so we don't need to add an additional argument in front of sys.argv. The argv[0] which is used in gem5 config scripts is the name of the config script itself. While it might seem a little odd for the name of a systemc program to end in .py, it's as arbitrary as any other name, and generally shouldn't cause a problem. If some other more sophisticated mechanism for setting argv[0] is necessary, then the user can write a very slightly more complicated version of this script with additional logic. Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8 Reviewed-on: https://gem5-review.googlesource.com/c/16342 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11systemc: configs: Add a very simple config which just runs sc_main.Gabe Black
This config will just run the sc_main function (which must have been provided in c++ somehow), passing through any of the scripts command line arguments to sc_main. Needing to do this sort of thing is common enough that there should be a canned config which supports it. Change-Id: I8f88ba4776b9ec919dd8145a58cd856e11ac4e77 Reviewed-on: https://gem5-review.googlesource.com/c/16287 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-07configs: Unifiy interpretation of Realview mem_regionsGiacomo Travaglini
In every arm platform which is making use of them, mem_regions are interpreted as a pair of start address and size. However arm SimpleSystem, which is using VExpress_GEM5_V1, is interpreting them as start address and end address. This patch is fixing this mismatch. Change-Id: I0b2a2193cd07fbc5430f233438269a9c7c353df9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16205 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-30configs: Enable DTB autogeneration in starter_fs.pyGiacomo Travaglini
This patch is removing hardcoded default DTBs in favour of common DTB autogeneration. Change-Id: I68fdc2a169bfa8e8657c9ed4e4e127957a08cca1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15959 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it. Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25configs: fs.py remove --generate-dtb and enable it by defaultCiro Santilli
The option is now enabled if neither --bare-metal nor --dtb-filename are given. This is what fs_bigLITTLE.py already did before this patch. Change-Id: I9179f8c9fa18edbd1e0f1a65ea2c1de0a26b7921 Reviewed-on: https://gem5-review.googlesource.com/c/15899 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-25configs, arch-arm: don't search for default DTB and kernelCiro Santilli
Before this commit, there were default magic DTB and kernel filenames for some platforms. This was inelegant and error prone, as it refered to out-of-tree files, and set defaults which users almost always want to customize with explicit command line options. One result of this is that a wrong exception could be thrown if --kernel was given but not --machine-type, since the default machine type VExpress_EMM had a default kernel, and the code would always search for the default filename even though --kernel was given: IOError: Can't find file 'vmlinux.aarch32.ll_20131205.0-gem5' on path. The defaults existed only for older machine types, and not for the usually recommended VExpress_GEM5_V1, which suggests that this deprecation should not affect many users. Change-Id: Ia49298304f658701ea0800bd79e08db404a655c3 Reviewed-on: https://gem5-review.googlesource.com/c/15898 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-09configs: Revamp ruby mem test to align with MemTestNikos Nikoleris
The test script was broken as it was based on an older version of MemTest, this changes revamps the creation of MemTest and removes parameters that are not any longer valid. Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13596 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-08configs: Add missing path to ruby importsDaniel R. Carvalho
Add missing addToPath to ruby files, so that import modules from previous folder are visible. Change-Id: I912d78a2f709974f72fe768e73abac1617126f46 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13995 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19config: add --param to fs.py, se.py and fs_bigLITTLE.pyCiro Santilli
The option allows to set SimObject params from the CLI. The existing config scripts have a large number of options that simply set a single SimObject parameter, and many still are not exposed. This commit allows users to pass arbitrary parameters from the command line to prevent the need for this kind of trivial option. Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944 Reviewed-on: https://gem5-review.googlesource.com/c/12985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-09configs: Fix CPUClass typo in se.pyDaniel R. Carvalho
Change 719eb033fe435133abf15501c249eec10d1c861f added a typo to se.py that breaks simpoint simulation, which generates the following error: Traceback (most recent call last): File "<string>", line 1, in <module> File "/home/daniel/gem5/src/python/m5/main.py", line 435, in main exec filecode in scope File "./configs/example/se.py", line 217, in <module> if not CpuConfig.is_atomic_cpu(TestCPUClass): NameError: name 'TestCPUClass' is not defined Change-Id: Ideede8c96a40ee16af733c3d57b02b64f1a18d12 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13267 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-17config, arm, power: Example to report the power for the L2 CacheSherif Elhabbal
This patch add an example to demonstrate how to report the power for the L2 Cache of the big cluster separately ,it decouples the L2 contributions from the CPU power equation Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58 Reviewed-on: https://gem5-review.googlesource.com/12684 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-12config, dev-arm: Fix UART handling baremetal modeCiro Santilli
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message: AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart' Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector. Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-10configs: Use the same address ranges for dir and mem_ctrlsNikos Nikoleris
In Ruby, for every directory we create one memory controller for every range in the memory ranges. Previously the memory controllers and the directories created their address ranges independently and as a result a mismatch was possible. In fact, we assinged an interleaved address range with hasing for the memory controllers while the corresponding directories would be assigned the same interleaved address range without hashing. This change uses the address range of the memory controllers to populate the list of address ranges for the corresponding directory and avoid bugs due to code duplication. Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a Reviewed-on: https://gem5-review.googlesource.com/12318 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-03config: Move KVM CPU checking to CpuConfig helper moduleAndreas Sandberg
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is somewhat involved since CPUs can be disabled at compile time. Enable better code reuse by moving it to the CpuConfig module. Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12418 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17configs: Always exit with code 0Jason Lowe-Power
Update simulation.py to always exit with code 0 assuming the simulation exits normally. If the running application has a return code that is non zero, then print the return code before exiting. Change-Id: I1983985d50311627574d4364b32ee961ae88e003 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4880
2018-07-13configs: Update the DRAM sweep script to use PyTrafficGenAndreas Sandberg
Instead of generating a text configuration, use the new Python-based traffic generator. Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11519 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-03-23learning_gem5: Add a simple config for MI_exampleJason Lowe-Power
Adds a new config script to configure the MI_example protocol. This script closely follows the script used for MSI, but instead supports the MI_example protocol. This script works with the simple_ruby runscript and can be included instead of msi_caches. Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8945 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Ruby random tester files for MSIJason Lowe-Power
Adds a pair of scripts to run the Ruby random tester with the MSI protocol. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html Change-Id: I15550a36618546f0354163b0216cf771f434ed84 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8944 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 09:26:36 +0000