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AgeCommit message (Expand)Author
2015-02-03config: Add XOR hashing to the DRAM channel interleavingAndreas Hansson
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
2015-01-30config: arm: fix os_flagsMalek Musleh
2015-01-20config, ruby: connect dma to networkMalek Musleh
2015-01-20scons: Do not build the InOrderCPUAndreas Hansson
2015-01-03arm: fix build_drive_system when not using default optionsAnthony Gutierrez
2015-01-03configs: ruby: removes bug introduced by 05b5a6cf3521Nilay Vaish
2014-12-23config: Expose the DRAM ranks as a command-line optionAndreas Hansson
2014-12-23config: Add --memchecker optionMarco Elver
2014-12-23config: Add options to take/resume from SimPoint checkpointsDam Sunwoo
2014-12-04config: Add two options for setting the kernel command line.Gabe Black
2014-12-04config: ruby: mi protocol: correct master slave setting for dmaNilay Vaish
2014-12-03config: Get rid of some extra spaces around default arguments.Gabe Black
2014-11-23config, kvm: Enabling KvmCPU in SE modeAlexandru Dutu
2014-11-23Backed out prior changeset f9fb64a72259Steve Reinhardt
2014-11-23config: ruby: Get rid of an "eval" and an "exec" operating on generated code.Gabe Black
2014-11-18configs: small fix to ruby portion of fs.py and se.pyNilay Vaish
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-11-06ruby: provide a backing storeNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-10-29arm, tests: Update config files to more recent kernels and create 64-bit regr...Ali Saidi
2014-10-29arm: fix bare-metal memory setup.Ali Saidi
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-11config: separate function for instantiating a memory controllerNilay Vaish
2014-10-11ruby: moesi hammer: correct typo in master-slave assignmentNilay Vaish
2014-07-17config, x86: Ensure that PCI devs get bridged to the memory busJiuyue Ma
2014-07-17config, x86: swap bus_id of ISA/PCI in X86 IntelMPTableJiuyue Ma
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20cpu: Update DRAM traffic genWendy Elsasser
2014-09-20cpu: use probes infrastructure to do simpoint profilingDam Sunwoo
2014-09-03arm: Support >2GB of memory for AArch64 systemsAli Saidi
2014-09-03arm: Assume we have a kernel that supports pci devicesAli Saidi
2014-09-03config: Refactor RealviewEMM to fit into new config systemGeoffrey Blake
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03mem: Add utility script to plot DRAM efficiency sweepAndreas Hansson
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-08-10config: Fix cache latency param in mem testRadhika Jagtap
2014-07-28arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2Anthony Gutierrez
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-06-30arm: make the bi-mode predictor the default for O3_ARM_v7a_BPAnthony Gutierrez
2014-05-15config: remove unecessary assignment of etherlink interfacesAnthony Gutierrez
2014-05-09config: Bump DRAM sweep bus speed to match DDR4 configAndreas Hansson
2014-04-19config: ruby: remove memory controller from network testNilay Vaish
2014-04-14arm: set default kernels for VExpress_EMM and VExpress_EMM64Anthony Gutierrez
2014-04-10config: add num-work-ids command line optionGedare Bloom
2014-04-01configs: use SimpleMemory when using ruby in se modeNilay Vaish
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson