| Age | Commit message (Collapse) | Author |
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old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
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--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
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namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
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it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
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build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
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Update copyright dates and author list
SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
Update copyright dates and author list
--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
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|
--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
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--HG--
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forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc:
Remove unused commented out code.
cpu/base_dyn_inst.hh:
Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
Reorder functions.
cpu/beta_cpu/commit_impl.hh:
Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
Remove commented code.
cpu/beta_cpu/full_cpu.cc:
Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
Use full path name for #defines.
cpu/beta_cpu/ras.hh:
Use full path names for #defines. Remove mod operation.
cpu/beta_cpu/regfile.hh:
Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Update programming style.
--HG--
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inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
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SConscript:
Include new files.
arch/alpha/isa_desc:
Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Fixes for gcc-3.4.
Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
Use new params pointer in BaseCPU.
Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
Remove unused global variable.
cpu/static_inst.hh:
Include OoODynInst for new lightweight OoO CPU
--HG--
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branch prediction, and makes memory dependence work properly.
SConscript:
Added return address stack, tournament predictor.
cpu/base_cpu.cc:
Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Register stats.
cpu/beta_cpu/alpha_params.hh:
Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
Removed one class.
cpu/beta_cpu/bpred_unit.hh:
Add in RAS, stats. Changed branch predictor unit functionality
so that it holds a history of past branches so it can update, and also
hold a proper history of the RAS so it can be restored on branch
mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
Added in stats, history of branches, RAS. Now bpred unit actually
modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
Add in sanity checks.
cpu/beta_cpu/comm.hh:
Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
Add in stats.
cpu/beta_cpu/commit_impl.hh:
Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
Stats.
cpu/beta_cpu/fetch.hh:
Stats, change squash so it can handle squashes from decode differently
than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
Add in stats. Change how a cache line is fetched. Update to work with
caches. Also have separate functions for different behavior if squash
is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
Added function to remove instructions from back of instruction list
until a certain sequence number.
cpu/beta_cpu/iew.hh:
Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
Debug stuff
cpu/beta_cpu/inst_queue.hh:
Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
Stats, change how mem dep unit works, debug stuff. Also add in
parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
Add in stats, change how memory dependence unit works. It now holds
the memory instructions that are waiting for their memory dependences
to resolve. It provides which instructions are ready directly to the
IQ.
cpu/beta_cpu/regfile.hh:
Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
Add in debugging statements.
cpu/beta_cpu/store_set.hh:
Reorder function arguments to match the rest of the calls.
--HG--
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Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
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caches.
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
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