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path: root/cpu/memtest/memtest.cc
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2005-04-11Make the notion of a global event tick independent of the actualNathan Binkert
CPU cycle ticks. This allows the user to have CPUs of different frequencies, and also allows frequencies and latencies that are not evenly divisible by the CPU frequency. For now, the CPU frequency is still set to the global frequency, but soon, we'll hopefully make the global frequency fixed at something like 1THz and set all other frequencies independently. arch/alpha/ev5.cc: The cycles counter is based on the current cpu cycle. cpu/base_cpu.cc: frequency isn't the cpu parameter anymore, cycleTime is. cpu/base_cpu.hh: frequency isn't the cpu parameter anymore, cycleTime is. create several public functions for getting the cpu frequency and the numbers of ticks for a given number of cycles, etc. cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/trace/trace_cpu.cc: Now that ticks aren't cpu cycles, fixup code to advance by the proper number of ticks. cpu/memtest/memtest.hh: cpu/trace/trace_cpu.hh: Provide a function to get the number of ticks for a given number of cycles. dev/alpha_console.cc: Update for changes in the way that frequencies and latencies are accessed. Move some stuff to init() dev/alpha_console.hh: Need a pointer to the system and the cpu to get the frequency so we can pass the info to the console code. dev/etherbus.cc: dev/etherbus.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ide_disk.hh: dev/ns_gige.cc: dev/ns_gige.hh: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. dev/ide_disk.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. Add some extra debugging printfs dev/platform.cc: dev/sinic.cc: dev/sinic.hh: outline the constructor and destructor dev/platform.hh: outline the constructor and destructor. don't keep track of the interrupt frequency. Only provide the accessor function. dev/tsunami.cc: dev/tsunami.hh: outline the constructor and destructor Don't set the interrupt frequency here. Get it from the actual device that does the interrupting. dev/tsunami_io.cc: dev/tsunami_io.hh: Make the interrupt interval a configuration parameter. (And convert the interval to the new latency/frequency stuff in the python) kern/linux/linux_system.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. kern/tru64/tru64_system.cc: For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. python/m5/config.py: Fix support for cycle_time relative latencies and frequencies. Add support for getting a NetworkBandwidth or a MemoryBandwidth. python/m5/objects/BaseCPU.mpy: All CPUs now have a cycle_time. The default is the global frequency, but it is now possible to set the global frequency to some large value (like 1THz) and set each CPU frequency independently. python/m5/objects/BaseCache.mpy: python/m5/objects/Ide.mpy: Make this a Latency parameter python/m5/objects/BaseSystem.mpy: We need to pass the boot CPU's frequency to the system python/m5/objects/Ethernet.mpy: Update parameter types to use latency and bandwidth types python/m5/objects/Platform.mpy: this frequency isn't needed. We get it from the clock interrupt. python/m5/objects/Tsunami.mpy: The clock generator should hold the frequency sim/eventq.hh: Need to remove this assertion because the writeback event queue is different from the CPU's event queue which can cause this assertion to fail. sim/process.cc: Fix comment. sim/system.hh: Struct member to hold the boot CPU's frequency. sim/universe.cc: remove unneeded variable. --HG-- extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-02-19Clean up CPU stuff and make it use params structsNathan Binkert
cpu/base_cpu.cc: cpu/base_cpu.hh: Convert the CPU stuff to use a params struct cpu/memtest/memtest.cc: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. Don't have any default parameters. cpu/memtest/memtest.hh: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. cpu/simple_cpu/simple_cpu.cc: Convert to use a params struct. remove default parameters cpu/simple_cpu/simple_cpu.hh: convert to use a params struct cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: this isn't really a cpu. don't derive from BaseCPU objects/MemTest.mpy: we only need one max_loads parameter sim/main.cc: Don't check for the number of CPUs since we may be doing something else going on. If we don't have anything to simulate, the simulator will exit anyway. --HG-- extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
2004-12-14Modified to work with do_eventsRon Dreslinski
No multiple requests to the same block outstanding from the same tester Using false sharing, each tester only access a single byte within the block based on which tester it is Allow more cycles before signalling deadlock, with do_events it may take some time with NACK/retry and many proccessors --HG-- extra : convert_revision : 4c8eab99082c53840a5ad2a926457dfc27f23b77
2004-11-18back out ron's memory system changes because they break dmaNathan Binkert
--HG-- extra : convert_revision : 3e0af11cd9dc97743f288cee5248fa44013baddd
2004-11-12Make changes so that coherence works on a timing bus for the top-level of ↵Ron Dreslinski
caches. This added a snoopResponse callback to the caches, and a NACK to requests. cpu/memtest/memtest.cc: Modified to work with do_events: No multiple requests to the same block outstanding at the same time from the same tester Using false sharing, each tester does only 1 byte access using it's id as the blk offset Allow for cycles before signaling deadlock, with do events it can take time to complete (NACK/blocked bus) cpu/memtest/memtest.hh: Updated to keep an id with each tester (used for address generation) Updated to keep a list of outstanding address to prevent multiple outstanding per tester //Should really look into doing store forwarding within the tester, then we can test more functionality --HG-- extra : convert_revision : 05fbcf547e4ffab9d220aeb73126ed787ca82239
2004-11-03Fix to deal with the new base class parameter for registrationNathan Binkert
deferral --HG-- extra : convert_revision : f968e3ba44604522cb10db8a60d7e18f1733e06a
2004-06-08Updated Copyright with information in bitkeeper changelogsAli Saidi
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/full_cpu/op_class.hh: cpu/full_cpu/smt.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/platform.cc: dev/platform.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.hh: dev/tsunamireg.h: docs/stl.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: sim/universe.cc: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/m5/m5.c: util/m5/m5op.h: util/tap/tap.cc: Updated Copyright dev/console.cc: dev/console.hh: This code isn't ours, and shouldn't have our copyright --HG-- extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
2004-05-21rename namespace Statistics to StatsNathan Binkert
--HG-- extra : convert_revision : 28f1703f8d7d8cf33fb952ae450f66bdba860fb7
2004-05-04Major stats package cleanupNathan Binkert
Add support for generic visitors for stats and use them to implement independent output functions. Support for mysql output and some initial code for hacking on mysql output with python arch/alpha/pseudo_inst.cc: base/hybrid_pred.cc: base/hybrid_pred.hh: base/sat_counter.cc: base/sat_counter.hh: cpu/simple_cpu/simple_cpu.cc: kern/tru64/tru64_events.cc: sim/main.cc: sim/process.cc: sim/process.hh: sim/sim_events.cc: sim/sim_object.cc: sim/system.hh: update for changes in stats package base/statistics.cc: move the python output code to base/stats/puthon.(cc|hh) and reimplement it as a visitor. move the text output code to base/stats/text.(cc|hh) and reimplement it as a visitor. move the database stuff into base/stats/statdb.(cc|hh) and get rid of the class. Put everything as globals in the Statistics::Database namespace. allocate unique ids for all stats. directly implement the check routine and get rid of the various dumping routines since they're now in separate files. make sure that no two stats have the same name clean up some loops base/statistics.hh: major changes to the statistics package again lots of code was factored out of statistics.hh into several separate files in base/stats/ (this will continue) There are now two Stat package types Result and Counter that are specified to allow the user to keep the counted type separate from the result type. They are currently both doubles but that's an experiment. There is no more per stat ability to set the type. Statistics::Counter is not the same as Counter! Implement a visitor for statistics output so that new output types can be implemented independently from the stats package itself. Add a unique id to each stat so that it can be used to keep track of stats more simply. This number can also be used in debugging problems with stats. Tweak the bucket size stuff a bit to make it work better. fixed VectorDist size bug cpu/memtest/memtest.cc: Fix up for changes in stats package Don't use value() since it doesn't work with binning. If you want a number as a stat, and to use it in the program itself, you really want two separate variables, one that's a stat, and one that's not. cpu/memtest/memtest.hh: Fix up for changes in stats package test/Makefile: Try to build stuff now that directories matter test/stattest.cc: test all new output types choose which one with command line options --HG-- extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
2004-02-17Add COW support to the IIC.Erik Hallnor
cpu/memtest/memtest.cc: Move the trace Addr to the end of the printouts --HG-- extra : convert_revision : 875f0a3f65e07f531a23fea6be07fbf3239ec2c4
2004-02-14Add full copy support.Erik Hallnor
cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Add 2 new parameters to control the percentage of unaligned copy sources and destinations. --HG-- extra : convert_revision : 2646ee2f195e9f3e76bc257b8716163ef63a9f40
2004-02-10Add support for multiple outstanding aligned copiesErik Hallnor
cpu/memtest/memtest.cc: Add traceBlockAddr to trace outputs. --HG-- extra : convert_revision : e4ebaf9647fb393448367f4f4af3bae566f51c24
2004-02-09Add LRU aligned copies to the hierarchy, with only one outstanding copy. ↵Erik Hallnor
Aligned copies now fully work in LRU (just need to write the IIC doCopy call). At the moment they are slow since a stalled copy stalls the entire cache. cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Add aligned copy tests, percent of copies is specified by percent_copies --HG-- extra : convert_revision : eaf1900fcb8832db98249e94e3472ebfb049eb48
2004-02-02Change MemReqPtr parameters to references.Steve Reinhardt
This avoids incrementing and decrementing the MemReq reference counters on every call and return. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: cpu/exec_context.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: dev/alpha_console.cc: dev/alpha_console.hh: Change MemReqPtr parameters to references. --HG-- extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
2003-11-06Various fixes to memory code.Erik Hallnor
cpu/memtest/memtest.cc: Disable probes until the work in all cases util/rundiff: Comment out Algorithm::Diff since its not needed. --HG-- extra : convert_revision : 40e76ae8926650986a170a0ba6ef331519aceb19
2003-10-22Probe is now in. You currently can't probe uncacheable (of course it doesn't ↵Erik Hallnor
make much sense either. Also, probe doesn't currently support compressed data, but will as soon as I encapsulate the calls more. cpu/memtest/memtest.cc: Change memtest to not do probes on uncacheables. --HG-- extra : convert_revision : 28ca4f793562e55da75e8b7fc3852bb5b1328ea9
2003-10-21Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5Erik Hallnor
--HG-- extra : convert_revision : 1fcdbd9d2efc1e0490716de46c81e94f4b28678b
2003-10-21memtest.cc:Erik Hallnor
Add probe calls to test update probe path. cpu/memtest/memtest.cc: Add probe calls to test update probe path. --HG-- extra : convert_revision : b0fb97b54b6ffce9c575fda680b778da63767b7c
2003-10-20Separate the stuff for SimObject from SimObject builder.Nathan Binkert
This makes testing a bit easier. arch/alpha/alpha_memory.cc: cpu/intr_control.cc: cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: dev/alpha_console.cc: dev/console.cc: dev/disk_image.cc: dev/etherbus.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ethertap.cc: dev/simple_disk.cc: kern/tru64/tru64_system.cc: sim/main.cc: sim/prog.cc: Need to include builder.hh sort #includes sim/sim_object.cc: sim/sim_object.hh: Separate the SimObjectBuilder stuff into its own file --HG-- extra : convert_revision : e8395e0cc6ae1f180f9cd6f100795a1ac44aeed5
2003-10-16Add a commited loads event queue similar to the one for commited instructions.Erik Hallnor
Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads. cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Swap out maxReads for the new commited loads model. --HG-- extra : convert_revision : 35031329bbc476122b2203104537a9f8b46addfa
2003-10-10Make include paths explicit and update makefile accordingly.Steve Reinhardt
arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/fake_syscall.cc: arch/alpha/faults.cc: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/circlebuf.cc: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/cprintf.cc: base/cprintf.hh: base/fast_alloc.cc: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/exec_aout.h: base/loader/exec_ecoff.h: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/pollevent.cc: base/pollevent.hh: base/random.cc: base/random.hh: base/range.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/statistics.cc: base/statistics.hh: base/str.cc: base/trace.cc: base/trace.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/console.cc: dev/console.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/simple_disk.cc: dev/simple_disk.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: sim/debug.cc: sim/eventq.cc: sim/eventq.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/prog.cc: sim/prog.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_object.cc: sim/sim_object.hh: sim/sim_time.cc: sim/system.cc: sim/system.hh: sim/universe.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/tap/tap.cc: Make include paths explicit. --HG-- extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
2003-10-10File moves for the reorg. Tree is in broken state until I commit the ↵Steve Reinhardt
makefile and #include changes. --HG-- rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh rename : sim/cache/null_compression.hh => base/compression/null_compression.hh rename : sim/hybrid_pred.cc => base/hybrid_pred.cc rename : sim/hybrid_pred.hh => base/hybrid_pred.hh rename : base/aout_object.cc => base/loader/aout_object.cc rename : base/aout_object.hh => base/loader/aout_object.hh rename : base/coff_sym.h => base/loader/coff_sym.h rename : base/coff_symconst.h => base/loader/coff_symconst.h rename : base/ecoff_object.cc => base/loader/ecoff_object.cc rename : base/ecoff_object.hh => base/loader/ecoff_object.hh rename : base/elf_object.cc => base/loader/elf_object.cc rename : base/elf_object.hh => base/loader/elf_object.hh rename : base/exec_aout.h => base/loader/exec_aout.h rename : base/exec_ecoff.h => base/loader/exec_ecoff.h rename : base/object_file.cc => base/loader/object_file.cc rename : base/object_file.hh => base/loader/object_file.hh rename : base/symtab.cc => base/loader/symtab.cc rename : base/symtab.hh => base/loader/symtab.hh rename : sim/predictor.hh => base/predictor.hh rename : sim/sat_counter.cc => base/sat_counter.cc rename : sim/sat_counter.hh => base/sat_counter.hh rename : sim/base_cpu.cc => cpu/base_cpu.cc rename : sim/base_cpu.hh => cpu/base_cpu.hh rename : sim/exec_context.cc => cpu/exec_context.cc rename : sim/exec_context.hh => cpu/exec_context.hh rename : sim/exetrace.cc => cpu/exetrace.cc rename : sim/exetrace.hh => cpu/exetrace.hh rename : sim/op_class.hh => cpu/full_cpu/op_class.hh rename : sim/smt.hh => cpu/full_cpu/smt.hh rename : sim/inst_seq.hh => cpu/inst_seq.hh rename : sim/intr_control.cc => cpu/intr_control.cc rename : sim/intr_control.hh => cpu/intr_control.hh rename : sim/memtest.cc => cpu/memtest/memtest.cc rename : sim/memtest.hh => cpu/memtest/memtest.hh rename : sim/pc_event.cc => cpu/pc_event.cc rename : sim/pc_event.hh => cpu/pc_event.hh rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh rename : sim/static_inst.cc => cpu/static_inst.cc rename : sim/static_inst.hh => cpu/static_inst.hh extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6