| Age | Commit message (Collapse) | Author |
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Ready to start testing if I could fix the linking errors I can't ever seem to fix.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add connecting of ports until builder can handle it.
mem/physical.cc:
Add function to allocate a port in the object
Remove some full_sys stuff untill needed
mem/physical.hh:
Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
Update the params
sim/process.cc:
Make sure to use the right name (hopefully CPU constructor already called)
--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
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CPU_MODELS parameter. For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.
SConscript:
Separate out cpu-model-specific files so they can be conditionally
included based on value of new CPU_MODELS parameter.
Most of these are now handled in cpu/SConscript, except for FullCPU
which is still in this file.
arch/SConscript:
The set of CPU-model-specific execute files must now be
determined from the CPU_MODELS parameter, via the new
cpu_models.py file.
Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
Move CpuModel definition and objects out to a
separate file so they can be shared with scons.
Global list of CPU models to generate code for is now
controlled by command-line parameters (so we can do
only a subset of the available ones).
build/SConstruct:
Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
Rename static_inst_impl.hh to static_inst_exec_sigs.hh.
--HG--
extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
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into zeep.eecs.umich.edu:/z/saidi/work/m5.head
cpu/simple/cpu.cc:
remove initCPU from constructor
dev/alpha_console.cc:
we are panicing, so no need to return a fault
--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
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Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.
arch/alpha/ev5.cc:
Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move the cpu initilization into an init() function since it now needs
the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
instead of the bootstrap variables, add space for 64 cpu stacks in the
alpha access structure.
sim/system.cc:
start all cpus immediately rather than just the first one
--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
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Clean out old memory python files, move them into old_mem directory. Maybe we should just delete them, they are under revision control.
Add new py files for new objects.
SConscript:
Update because memory is just a header file now
base/chunk_generator.hh:
Make Chunk Generator return the entire size if the chunk_size is set to zero. Useful when trying to chunck on blocksize of memory, which can write large pieces of data.
cpu/simple/cpu.cc:
Make sure to delete the pkt.
mem/physical.cc:
mem/physical.hh:
Set up response event.
mem/port.cc:
Rename rqst to req to conform to same standard naming convention.
python/m5/objects/PhysicalMemory.py:
Update the params, inheritence
--HG--
extra : convert_revision : 857154ec256522baf423b715833930497999549b
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arch/mips/faults.hh:
remove nonsense
arch/mips/isa/base.isa:
define R31
arch/mips/isa/bitfields.isa:
forgotten bitfields
arch/mips/isa/decoder.isa:
INT64 -> int64_t
arch/mips/isa/formats.isa:
fix comments
arch/mips/isa/formats/branch.isa:
Branch -> BranchLikely
RB -> RT
arch/mips/isa/formats/fp.isa:
Make FP ops generates
arch/mips/isa/formats/mem.isa:
RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
Rc -> Rd
arch/mips/isa/formats/util.isa:
forgot brace and semicolon
arch/mips/isa/includes.isa:
remove unnecessary files
arch/mips/isa_traits.hh:
spacing
cpu/static_inst.hh:
add cond_delay_slot flag
--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
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Pull opClassStrings array out of encumbered/cpu/full/fu_pool.cc and move to
new cpu/op_class.cc file.
SConscript:
Add new cpu-model-independent file to define OpClass enum strings.
cpu/op_class.hh:
Fix comments etc.
cpu/static_inst.hh:
op_class.hh moved to cpu directory
--HG--
rename : encumbered/cpu/full/op_class.hh => cpu/op_class.hh
extra : convert_revision : 314ac5ab7cc5c6a34b43dc1c2f2adc3e02f6d07f
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old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
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clean up implementation a little.
SConscript:
Add mem/port.cc
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move read/writeBlob functions to base Port class.
mem/port.hh:
Implement read/writeBlob functions.
No need for them to be virtual since the proxy
object (now called TranslatingPort) is not a
subclass of Port.
mem/port.cc:
Implement read/writeBlob functions.
--HG--
extra : convert_revision : a3660eaa43a7c286aca962f17fa32fbd42bf1fa6
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--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
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cases. Still have some duplicated code we may want to revisit.
cpu/simple/cpu.cc:
Thanks to Ali I found the chunk generator, although I still seem to be duplicating some code becuase the only difference between readBlob and writeBlob is the command in the packet. Perhaps an access function with the command as a param would help with the duplication (sendBlob that takes a cmd (maybe).
mem/translating_port.cc:
Using the chunck generator to break it up to be in page size chunks
--HG--
extra : convert_revision : cc2e4e60c76098655e469f81c89d2c7438350fdb
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stever wrote to break up address ranges into blk/page size chunks.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add read/write blob definitions, still need to break it up into blk size chunks (where was the code stever wrote for that?)
mem/physical.hh:
Remove un-needed function (I think)
mem/port.hh:
Default these virtual functions to panic unimplented
mem/translating_port.cc:
Again handling read/write string properly.
Need the stever code to break things into page size chunks yet
mem/translating_port.hh:
Having trouble with the const declerator. I will need to read how it works, for now it compiles if I remove it.
--HG--
extra : convert_revision : f174e06700daa9967958d18e01798270c90d6dac
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Now I need to fix linking errors, probably due to missing function details in new memory objects.
cpu/exec_context.cc:
cpu/exec_context.hh:
Fix constructor for SE mode
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Fix compilation errors
--HG--
extra : convert_revision : 6a58c0906340e10b654369c36f528fc17e3f19be
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via the page table before accessing the memory port.
Other compile issues cleaned up.
SConscript:
Changes to compile the new Translating Port.
Split out memtester and eio support, will rework them back in after first getting a simpleCPU to work
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Changes to use the new translating Port.
cpu/exec_context.cc:
cpu/exec_context.hh:
Create a translating port in each execution context.
sim/process.cc:
Fix the way we do proxy memory
--HG--
extra : convert_revision : 3d33218fe8b425a5d9ce24757f1112b4aa6001fd
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into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class deiffinitions
--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
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cpu/base.hh:
cpu/static_inst.hh:
Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh
cpu/exec_context.hh:
Changed Fault back to Fault *
--HG--
extra : convert_revision : 410f2e2472f8aa5bf92619a5defdf85f689a5597
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into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
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namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
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arch/mips/isa/formats/branch.isa:
add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
change from mergedmem
--HG--
extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
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Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.
arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
Remove fake fault.
arch/alpha/faults.cc:
Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
Remove fake fault, change pointers to const pointers.
--HG--
extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
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it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
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Should we add a proxy_port that does the v->p address translation?
Should the proxy port return a fault on translation errors, if we add one?
arch/alpha/alpha_linux_process.cc:
Syscalls use a memPort through the CPU now instead of a xc functional memory.
cpu/base.hh:
Add a pointer to the memPort syscalls will use. Should this be a proxy_port that does address translation?
cpu/exec_context.cc:
cpu/exec_context.hh:
Remove functional memory from the exec context
cpu/simple/cpu.cc:
Set the memPort to be used as the syscall port as the dcache port
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Syscalls use a memPort through the CPU now instead of a xc functional memory.
Also, fix the fact that readStringFunctional doesn't return a fault... should proxy_port handle this because it is doing the translation?
--HG--
extra : convert_revision : 1f65318c6594301a75dc4dc0c99fdd436b094a7f
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fixing things, partly by ignoring CPU models
that don't currently compile.
SConscript:
Split sources for fast, simple, and o3 CPU models into
separate source lists. For now none of these are included
in the base source list, so you won't get any CPU models
at all... but we still can't compile the other stuff so
it's not an issue.
Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
FunctionalMemory -> Memory
cpu/pc_event.hh:
Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move Port functions into .cc file.
mem/port.hh:
Make recvAddressRangesQuery panic by default instead
of being abstract... do CPUs need to implement this?
mem/request.hh:
Add prefetch flags.
sim/syscall_emul.hh:
Start to fix...
--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
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compile decoder.cc but fails still.
SConscript:
Place the memory objects back in the right place
arch/alpha/isa_desc:
Fix includes to point to the new memory requests
cpu/exec_context.hh:
Exec context now points to memory object, fix the include paths.
Convert to prot_read/prot_write functions instead of read and write.
Convert to new CpuRequestPtr instead of MemReqPtr.
mem/request.hh:
Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence.
sim/process.hh:
Converted to point to new memory objects
--HG--
extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
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fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
targetarch/isa_traits.hh is now included through arch/isa_traits.hh
vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
Fixed the assert in the equals operator.
Changed the AlphaISA namespace reference to TheISA.
Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
Added an include of arch/isa_traits.hh so that TheISA would be defined.
--HG--
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arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
I much cleaner way to get max int
sim/syscall_emul.hh:
fix stat64 problems on *BSD
--HG--
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the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
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supports the response path of the new memory system, as well as retrying accesses.
cpu/simple/cpu.cc:
Update for new memory system. Supports using ports to access the memory system. The IcacheMissStall/DcacheMissStall statuses have been changed to reflect the cache returning a response after a variable latency (due to hit/miss). They are now DcacheWaitResponse/IcacheWaitResponse. Also supports retrying accesses.
For now the body of the copy functions are commented out.
cpu/simple/cpu.hh:
Update for new memory system.
--HG--
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The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Added the endianness namespace. This may change.
cpu/exec_context.hh:
Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
Forced LittleEndianness for lack of a better solution.
--HG--
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--HG--
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cpu/simple/cpu.cc:
Initialize the ports, also add Request and Packet instead of MemReq. Initial work at ICache read in place.
cpu/simple/cpu.hh:
Need to call the completion handler when we see a recieve.
--HG--
extra : convert_revision : a52caee6f0ceb5d9ee1e5acca63a202f5ea71359
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anymore
cpu/simple/cpu.hh:
Some needed includes
mem/port.hh:
Now we removed the sendResult and replaced with void,tick,bool don't need it defined anymore
--HG--
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cpu/simple/cpu.hh:
Adding port definitions to simple cpu, still needs work.
mem/bus.hh:
no return for void functions
--HG--
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Needed in the interim until we port the old model over
to the new interface. Long term we should have a cleaner
solution for controlling which models get compiled in.
SConscript:
Move old FullCPU source file list to separate full_cpu_sources
list so we can choose to not include it in compile.
arch/isa_parser.py:
Hack to avoid generating FullCPU execute files.
Need a better way to control this.
cpu/exetrace.cc:
Don't include old FullCPU-specific headers (apparently
unnecessary anyway--or if not they should be).
--HG--
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System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
Take System argument in constructor.
cpu/exec_context.cc:
Take System argument in constructor.
Merge two constructors into a single one.
cpu/exec_context.hh:
Take System argument in constructor.
Merge two constructors into a single one.
Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
Segregate full-system only Process parameters (most of them!).
sim/process.cc:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
Generate ProxyMemory object to pass to loader for transparent
virtual page allocation.
sim/process.hh:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
sim/system.cc:
sim/system.hh:
Enable System object for non-full-system too.
Basically involved putting most of the existing code
inside '#ifdef FULL_SYSTEM'.
Key thing needed for syscall emulation at this point is
the PhysicalMemory object (for Process initialization).
--HG--
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arch/alpha/alpha_tru64_process.cc:
base/intmath.hh:
base/statistics.cc:
base/str.cc:
cpu/o3/btb.cc:
sim/process.cc:
sim/syscall_emul.hh:
Rename intmath.hh functions to follow m5 style
(RoundUp -> roundUp, etc.).
base/intmath.cc:
Rename intmath.hh functions to follow m5 style
(RoundUp -> roundUp, etc.).
Also reindent code in m5 style.
--HG--
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cpu/simple/cpu.cc:
Properly set the Instruction Read bit in the Memory Request
--HG--
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is going away
--HG--
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cpu/profile.hh:
Add a placeholder for a reset callback
--HG--
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cpu/profile.hh:
use Counter for the profile count to avoid overflow
--HG--
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profileNode if we got a new one
cpu/simple/cpu.cc:
Only update the exec context's profileNode if we got a new one
--HG--
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are more efficient and reduce the number of new/delete calls
arch/alpha/stacktrace.cc:
- Change the StackTrace code so that the class can more easily be
cleaned out and reused to avoid extra allocations.
- Allow trace() to accept a static instruction pointer so it can
determine if the instruction is worth tracing. This is moved from
the CPU.
- provide constants for special meaning PCs (user, console, unknown),
instead of magic numbers
- switch to using kernelSymtab instead of allSymtab which will be
going away
- if the stack adjustment doesn't make any sense, exit and push
unknown so we don't get into an infinite loop or record garbage.
- check to see if we've made too many iterations through the stack
and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
- Change the StackTrace code so that the class can more easily be
cleaned out and reused to avoid extra allocations.
- Allow trace() to accept a static instruction pointer so it can
determine if the instruction is worth tracing. This is moved from
the CPU.
- provide constants for special meaning PCs (user, console, unknown),
instead of magic numbers
cpu/base.cc:
only clear the profile if we have one
include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
no need to include cpu/profile.hh here
cpu/profile.cc:
use ProfileNode pointers instead of objects in the ChildList
Consume a vector of addresses since that's really all we
care about.
cpu/profile.hh:
Keep pointers to ProfileNodes to reduce the size of these structures
keep a StackTrace around so that we may reuse it.
provide consume functions that use the new StackTrace trace interface
one consume function is inline and tries to fastpath the no trace
condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
include cpu/profile.hh here since base.hh no longer does
use the new FunctionProfile::consume interface
(which contains the tracing functions)
--HG--
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cpu/exetrace.cc:
CPU system name check doesn't work under syscall emulation, so don't
compile it in.
--HG--
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--HG--
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SConscript:
Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
Add profiling stuff
kern/kernel_stats.hh:
Use a smart pointer
sim/system.cc:
sim/system.hh:
Create a new symbol table that has all of the symbols for a
particular system
util/stats/categories.py:
change around the categories, add categories for function
profiling stuff
util/stats/profile.py:
No profile parsing and display code to deal with function
profiling stuff, graph, dot, and text outputs.
--HG--
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Intel sim compatible format.
--HG--
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cpu/memtest/memtest.cc:
Call random() consistently (not sometimes rand() and sometimes random()).
Don't bother to call random() for copy-only parameters unless we're
actually doing a copy.
--HG--
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including automatically fixing up addresses to deal with
optionally executed Alpha gp update prolog.
SConscript:
Remove freebsd_events.cc and linux_events.cc.
base/remote_gdb.cc:
cpu/pc_event.cc:
kern/system_events.cc:
kern/system_events.hh:
PCEvents now schedule themselves in constructor.
cpu/pc_event.hh:
PCEvents now schedule themselves in the constructor.
Get rid of constructor versions that don't take an address and
all the schedule() methods that are now unnecessary.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
Use new System methods to schedule function-based events.
Move FreeBSD-specific function event classes into FreebsdSystem.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
Use new System methods to schedule function-based events.
Move Linux-specific function event classes into LinuxSystem.
kern/tru64/tru64_events.hh:
PCEvents now schedule themselves in constructor.
Add DebugPrintfrEvent to encapsulate raw setting as new type
(to work better with new System function-event method.)
kern/tru64/tru64_system.cc:
Use new System methods to schedule function-based events.
kern/tru64/tru64_system.hh:
Add DebugPrintfrEvent to encapsulate raw setting as new type
(to work better with new System function-event method.)
sim/system.cc:
sim/system.hh:
Add functions to set up function-based events, including
automatically fixing up addresses to deal with optionally
executed Alpha gp update prolog.
--HG--
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build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
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SConscript:
Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
Replaced htoa() with gtoh().
dev/disk_image.cc:
Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
Got rid of magic numbers.
Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
Got rid of unnecessary macros.
Changed RegType_t to IdeRegType.
Changed bmi_regs to allow accessing registers by name instead of just by array index.
Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
Made ReadConfig and WriteConfig begin with a lower-case letter.
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
Added classes for RTC and PIT modules.
dev/tsunamireg.h:
Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
Got rid of a magic number.
Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
Replaced htoa() with htog().
python/m5/objects/Pci.py:
PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
TsunamiFake was renamed as IsaFake.
sim/system.cc:
Replaced htoa()s with htog()s.
dev/isa_fake.cc:
New BitKeeper file ``dev/isa_fake.cc''
TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
New BitKeeper file ``dev/isa_fake.hh''
TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
New BitKeeper file ``dev/pitreg.h''
Useful macros for working with PIT (Periodic Interval Timer) registers.
--HG--
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