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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
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cpu
Age
Commit message (
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Author
2004-06-23
Merge zizzer:/bk/linux into zeep.eecs.umich.edu:/z/saidi/work/m5-endian
Ali Saidi
2004-06-22
pull from head before pushing linux tree
Ali Saidi
2004-06-21
Merge saidi@zizzer.eecs.umich.edu:/bk/linux
Ali Saidi
2004-06-21
start towards getting m5 endian compliant
Ali Saidi
2004-06-17
Serialized cpu interrupts
Ali Saidi
2004-06-15
Merge isabel.reinhardt.house:/z/stever/bk/m5-head
Steve Reinhardt
2004-06-15
Get software prefetching to work in full-system mode.
Steve Reinhardt
2004-06-13
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
Erik Hallnor
2004-06-13
Add some rewritten trace readers.
Erik Hallnor
2004-06-10
lift common code *kernel_stats.* into the kern directory.
Lisa Hsu
2004-06-10
lif kernelt stats out of tru64 directory
Lisa Hsu
2004-06-08
Tracing now works for upto 4 threads. Easy change to get it to work for more,...
Erik Hallnor
2004-06-08
Add the capability to read and write memory trace files. Currently is cycle a...
Erik Hallnor
2004-06-08
Updated Copyright with information in bitkeeper changelogs
Ali Saidi
2004-06-01
Merge saidi@zizzer:/z/m5/Bitkeeper/m5/
Ali Saidi
2004-06-01
Added ability to specify system type/revision in config file. This
Ali Saidi
2004-05-31
Renamed OpClass enum members: they all end in 'Op' now.
Steve Reinhardt
2004-05-31
Merged head into linux tree
Ali Saidi
2004-05-28
Merged in new FastCPU stuff with existing code.
Kevin Lim
2004-05-27
FastCPU model added. It's very similar to the SimpleCPU, just without a lot ...
Kevin Lim
2004-05-21
add a few statistics events
Nathan Binkert
2004-05-21
rename namespace Statistics to Stats
Nathan Binkert
2004-05-21
Change the namespace Statistics to Stats
Nathan Binkert
2004-05-18
Add a level of indirection to the register accessors used in
Steve Reinhardt
2004-05-18
Replace explicit xc->misspeculating() tests in execute() methods
Steve Reinhardt
2004-05-18
merge m5 with linux for the event and binning lifting
Lisa Hsu
2004-05-17
Significant changes to ISA description to completely factor
Steve Reinhardt
2004-05-13
remove the annotation junk
Nathan Binkert
2004-05-12
Make a new stat type of Value which is a scalar stat that
Nathan Binkert
2004-05-11
first pass at merging m5 with linux
Lisa Hsu
2004-05-10
Do a better job of factoring out CPU model in ISA description.
Steve Reinhardt
2004-05-06
Whole mess'o'changes.. see individual files
Andrew Schultz
2004-05-04
Major stats package cleanup
Nathan Binkert
2004-04-03
More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
Steve Reinhardt
2004-04-02
Basic cleanup pass to get rid of a few things that made the Python
Steve Reinhardt
2004-03-24
Minor cleanup from building & diffing behavior
Steve Reinhardt
2004-03-11
merge with m5 head
Lisa Hsu
2004-03-05
fix ALPHA
Lisa Hsu
2004-03-05
changes that affect post checkpoint runs.
Lisa Hsu
2004-03-05
nother fix
Lisa Hsu
2004-03-05
serialization for binning. it is WAAAAAAAY past my bedtime.
Lisa Hsu
2004-03-04
Automerged
Erik Hallnor
2004-03-04
Copy implementations
Erik Hallnor
2004-02-29
Fix the swichover code. It's only for FULL_SYSTEM
Nathan Binkert
2004-02-29
fix switchover WRT interrupts
Nathan Binkert
2004-02-29
Initial cleanup pass of lisa's function call tracking
Nathan Binkert
2004-02-27
Added copy instructions to the ISA. Well it didn't break anything yet...
Erik Hallnor
2004-02-27
Initial copy support in the pipeline. Add copypal counting.
Erik Hallnor
2004-02-26
Make SW prefetch flag a parameter again, and add code to make
Steve Reinhardt
2004-02-24
add in an init() callback for CPU's so that no stats are accessed prior to th...
Lisa Hsu
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