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--HG--
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way a Tru64 system can be either Tlaser (by default) or Tsunami.
Added debugSymbolTable to Tru64 for symbol printing in InstExec Trace
cpu/exetrace.cc:
Fixed bug if debugSymbolTable doesn't exist, we shouldn't try to
look something up in it.
kern/tru64/tru64_system.hh:
Added ability to specify system type/revision in config file. This
way a Tru64 system can be either Tlaser (by default) or Tsunami.
--HG--
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Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.
arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
Renamed OpClass enum members.
--HG--
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base/stats/mysql.hh:
Rename of Statsistics namespace to stats... merge from head
--HG--
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arch/alpha/ev5.cc:
Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
Merged in changes to remove CPU dependence.
arch/isa_parser.py:
Merged in changes.
cpu/static_inst.hh:
Includes FastCPU execute methods.
--HG--
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of the stats tracking.
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.
arch/alpha/alpha_memory.cc:
The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
Moved code that once existed within simpleCPU to ev5, and templatized it.
This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
Added declaration for execute() using FastCPUExecContext.
--HG--
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arch/alpha/ev5.cc:
Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
add events for uncached reads/writes
--HG--
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--HG--
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--HG--
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instruction execute methods. Register i now means the instruction's
i'th src (or dest) operand, not architectural register i. Current
models that use the architectural reg index can look that up easily
in the instruction object. Future models that do register renaming
should find this much simpler to deal with.
arch/isa_parser.py:
Generate register accessors with an extra level of indirection.
cpu/simple_cpu/simple_cpu.hh:
Modify register accessors to use an extra level of indirection.
--HG--
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with an IsNonSpeculative flag.
No effect on results of non-full-system or SimpleCPU.
Very small impact on full-system FullCPU runs since old wrong-path
call_pal insts used to change the PC, where now they're treated
as no-ops.
arch/alpha/isa_desc:
Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead.
cpu/static_inst.hh:
Add IsNonSpeculative flag and isNonSpeculative() method to test it.
--HG--
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--HG--
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out CPU model. ISA description now generates multiple
output source files to (in theory) reduce compilation time.
arch/alpha/isa_desc:
Update for parser changes. Move most constructors
out of class declarations (which are now in decoder.hh)
and into decoder.cc. Move all execute() methods into
exec output.
arch/isa_parser.py:
Significant changes to make ISA description completely
independent of CPU model, and isolate model-dependent parts
of parser into one little class (CpuModel). Also split up code
output into multiple files (a header, a main source file, and
per-cpu execute() method files).
Noticeable changes to language as a result. See updated Doxygen
documentation.
cpu/simple_cpu/simple_cpu.hh:
SimpleCPUExecContext typedef no longer needed.
Add forward declaration of Process.
cpu/static_inst.hh:
SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
Make eaCompInst() and memAccInst() return const refs.
--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
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arch/alpha/isa_desc:
remove the annotation junk
Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
remove the annotation junk
add pseudo instruction code that was previously misplaced
--HG--
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proxies for a real C/C++ scalar value or scalar functor.
This replaces the scalar() and functor() terms that were
previously used in formulas. This helps when dumping
statistics because the formulas are not supposed to change.
cpu/base_cpu.cc:
Add a number of cycles stat to the cpu object that tracks the
number of cycles that the cpu has executed. This starts to pave
the way for cpu cycles being different from event ticks.
cpu/base_cpu.hh:
provide a functor for calculating all simulated instructions
of all CPUs and a virtual function for determining that number.
To deal with the change from functor() to Value::functor()
cpu/simple_cpu/simple_cpu.cc:
simTicks -> numCycles
numInsts is now a real Scalar stat, not a Formula
cpu/simple_cpu/simple_cpu.hh:
numInsts is now a real Scalar stat, not a Formula
count all instructions
sim/stat_control.cc:
simInsts, simTicks, hostMemory, and hostSeconds are no
longer Statistics::Formula but rather Statistics::Value
add new stat for tick frequency
sim/stats.hh:
don't need everything to be extern.
test/Makefile:
Make stuff work a tad bit better
test/stattest.cc:
test out Statistics::Value
--HG--
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--HG--
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(Still not perfect though.)
arch/alpha/isa_desc:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file. Force all instruction
execution context into a single model-dependent class (SimpleCPU itself
for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file.
Also restructure top level to allow parser to run under interactive
interpreter session for easier debugging.
cpu/exec_context.hh:
Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
StaticInst::execute no longer takes a CPU and an ExecContext,
just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
Add methods to redirect calls to ExecContext so SimpleCPU
can act as sole instruction execution context for itself.
Typedef SimpleCPU to SimpleCPUExecContext.
--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
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arch/alpha/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
base/loader/symtab.cc:
base/loader/symtab.hh:
cpu/exetrace.cc:
Changed InstExec traces to always print a symbol name
dev/ide_ctrl.cc:
dev/ide_disk.cc:
Tabs
dev/ide_disk.hh:
Change buffer size
dev/tsunami_pchip.cc:
Fix translatePciToDma to support scatter gather mapping
kern/linux/linux_system.cc:
Force simulator to wait until remote debugger attaches (should be removed
or turned on/off with a flag)
--HG--
extra : convert_revision : 1d08aebe3f448c87a963dd613de3e2e0cff0d48d
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Add support for generic visitors for stats and use them
to implement independent output functions.
Support for mysql output and some initial code for hacking
on mysql output with python
arch/alpha/pseudo_inst.cc:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/sat_counter.cc:
base/sat_counter.hh:
cpu/simple_cpu/simple_cpu.cc:
kern/tru64/tru64_events.cc:
sim/main.cc:
sim/process.cc:
sim/process.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/system.hh:
update for changes in stats package
base/statistics.cc:
move the python output code to base/stats/puthon.(cc|hh)
and reimplement it as a visitor.
move the text output code to base/stats/text.(cc|hh) and
reimplement it as a visitor.
move the database stuff into base/stats/statdb.(cc|hh) and
get rid of the class. Put everything as globals in the
Statistics::Database namespace.
allocate unique ids for all stats.
directly implement the check routine and get rid of the
various dumping routines since they're now in separate files.
make sure that no two stats have the same name
clean up some loops
base/statistics.hh:
major changes to the statistics package again
lots of code was factored out of statistics.hh into several
separate files in base/stats/ (this will continue)
There are now two Stat package types Result and Counter that
are specified to allow the user to keep the counted type
separate from the result type. They are currently both doubles
but that's an experiment. There is no more per stat ability to
set the type. Statistics::Counter is not the same as Counter!
Implement a visitor for statistics output so that new output
types can be implemented independently from the stats package
itself.
Add a unique id to each stat so that it can be used to keep
track of stats more simply. This number can also be used in
debugging problems with stats.
Tweak the bucket size stuff a bit to make it work better.
fixed VectorDist size bug
cpu/memtest/memtest.cc:
Fix up for changes in stats package
Don't use value() since it doesn't work with binning. If you
want a number as a stat, and to use it in the program itself,
you really want two separate variables, one that's a stat,
and one that's not.
cpu/memtest/memtest.hh:
Fix up for changes in stats package
test/Makefile:
Try to build stuff now that directories matter
test/stattest.cc:
test all new output types
choose which one with command line options
--HG--
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Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
--HG--
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configuration unnecessarily awkward. Biggest changes are:
- External and internal object names now match in all cases. The
macros still allow them to be different; the only reason I didn't
get rid of that is that the macros themselves should be going away
soon. In the few conflicting cases, I sometimes renamed the C++ object
and sometimes renamed the config object. The latter sets of substitions
are:
s/BaseBus/Bus/;
s/MemoryObject/FunctionalMemory/;
s/MemoryControl/MemoryController/;
s/FUPool/FuncUnitPool/;
- SamplingCPU is temporarily broken... we need to change the model
of how this works in the .ini file. Having it as a CPU proxy is
really awkward.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/process.cc:
Rename objects to match config name.
cpu/base_cpu.cc:
Uncomment SimObject define since SamplingCPU no longer
does this for us.
dev/ethertap.cc:
Use unsigned instead of uint16_t for params.
kern/tru64/tru64_system.cc:
Use unsigned instead of uint64_t for init_param param.
test/paramtest.cc:
Fix old SimObjectParam.
--HG--
extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc
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on various platforms.
base/hashmap.hh:
gcc on Alpha doesn't always define __LP64__,
even though it arguably should.
cpu/exec_context.cc:
Clear register file on non-full-system too (even though
it typically gets overwritten by the initial regs from
the Process object).
sim/process.cc:
Clear initial register copy in Process object.
Not all regs get initialized when the executable is loaded.
--HG--
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--HG--
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cpu/exec_context.cc:
put this code between #ifdef FULL_SYSTEM
--HG--
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cpu/exec_context.cc:
you can't delete an element of an array that you newed. oops.
kern/tru64/tru64_events.cc:
changes to reflect .ini changes, and also b/c es_intr and ipintr can happen at ANY point, even within a current calling path being tracked.
sim/system.cc:
can't delete an element of a newed array. must new them separately.
--HG--
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cpu/exec_context.cc:
nother little bug...forgot to pop off stack as i read off it
sim/system.cc:
forgot to pop off stack as i read off it
--HG--
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cpu/exec_context.cc:
sim/system.cc:
sim/system.hh:
serialization for binning
--HG--
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--HG--
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arch/alpha/isa_desc:
Need to return fault for copy operations.
cpu/exec_context.hh:
Add temporary storage to pass source address from copy load to copy store
cpu/simple_cpu/simple_cpu.cc:
Implement copy functions.
cpu/simple_cpu/simple_cpu.hh:
Return fault
--HG--
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cpu/base_cpu.cc:
#ifdef FULL_SYSTEM
--HG--
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cpu/base_cpu.cc:
gah! copy the interrupt status on switchover
--HG--
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code.
base/statistics.hh:
We're getting rid of FS_MEASURE, but for now, we're going
to still use a compile time flag to turn on and off binning
of statistics. (The flag is STATS_BINNING)
cpu/exec_context.cc:
cpu/exec_context.hh:
kern/tru64/tru64_system.cc:
get rid of FS_MEASURE
cpu/simple_cpu/simple_cpu.cc:
yank the function call tracking code out of the cpu and move
it into the software context class itself.
kern/tru64/tru64_system.hh:
get rid of FS_MEASURE
move all of the tacking stuff to the same place.
sim/system.hh:
cleanup
--HG--
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arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
--HG--
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arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
--HG--
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it actually do something on FullCPU. Still disabled, as it
causes detailed-boot to hang when you turn it on.
arch/alpha/isa_desc:
Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
Changed prefetch() return type from Fault to void.
--HG--
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the end of the build process. (Done by doing the registerExecContext() calling sequence in the init() process rather than the create() process).
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
same thing for simple cpu's.
--HG--
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cpu/simple_cpu/simple_cpu.cc:
Allow requests to be uncacheable
--HG--
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cpu/memtest/memtest.cc:
Move the trace Addr to the end of the printouts
--HG--
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arch/alpha/alpha_memory.cc:
SCCS merged
--HG--
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in adaptec_ctrl.hh
cpu/base_cpu.cc:
changed index to 64bits
cpu/base_cpu.hh:
changed index to 64 bits
--HG--
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cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Add 2 new parameters to control the percentage of unaligned copy sources and destinations.
--HG--
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into zizzer.eecs.umich.edu:/z/alschult/linux
--HG--
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cpu/memtest/memtest.cc:
Add traceBlockAddr to trace outputs.
--HG--
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arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
Merge
--HG--
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--HG--
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Aligned copies now fully work in LRU (just need to write the IIC doCopy call). At the moment they are slow since a stalled copy stalls the entire cache.
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Add aligned copy tests, percent of copies is specified by percent_copies
--HG--
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--HG--
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/kernel
--HG--
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execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
--HG--
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The last change only caught the ones with types that
started with capitals. This pass catches the rest
(mostly STL and uint*_t types).
base/cprintf_formats.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/serialize.cc:
sim/serialize.hh:
Change "foo_t& foo" to "foo_t &foo".
--HG--
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