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into zamp.eecs.umich.edu:/z/ktlim2/m5
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SConscript:
Remove efence option from automatically being used.
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output files and the output directory are are handled. Make
the output directory configuration via a command line parameter,
or an environment variable.
SConscript:
Add new output file stuff
base/misc.cc:
dev/simconsole.cc:
use new output file code
cpu/base_cpu.cc:
use new output file code to generate output streams
dev/etherdump.cc:
use the output file code to find the output directory
use a real stream instead of a pointer
dev/etherdump.hh:
use a real stream instead of a pointer
objects/Root.mpy:
output_dir and config_output_file are not longer configured here.
sim/main.cc:
- Completely rework the command line argument passing to deal with
changes in python and output files.
- Update help output to reflect changes.
- Remove all direct support for .ini files. They are strictly
for intermediate representation.
- Remove the --foo:bar=blah syntax for .ini files and add --foo.bar=blah
syntax for python. This will generate: foo.bar = 'blah' in the python
script.
- Add '-d' to set the output directory.
- Use new output file code to access the output stream.
sim/serialize.cc:
use the new code to find the output directory
sim/universe.cc:
Get rid of makeOutputStream. Use the new output file code.
Remove output_dir and config_output_file as parameters.
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address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
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changes come from templated code,
which is evaluated slightly differently than in previous versions of gcc.
arch/alpha/alpha_linux_process.cc:
Alphabetize includes.
arch/alpha/vptr.hh:
Change the constants that are being used for alpha pagebytes to come from the ISA.
base/random.hh:
cpu/static_inst.cc:
sim/param.cc:
Fix up template syntax.
base/range.hh:
Include iostream for << operator.
base/res_list.hh:
base/statistics.hh:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.hh:
sim/eventq.hh:
sim/param.hh:
Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the
function/variable until actual instantiation time by making it dependent on the templated class/function.
base/trace.cc:
Fix call to new.
base/trace.hh:
Fix up #define to have full path.
cpu/base_cpu.cc:
Fix up call to new.
dev/etherlink.hh:
dev/ns_gige.hh:
dev/sinic.hh:
Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as
a friend class.
dev/pcidev.hh:
Fix up re-definition of access level to params.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
Fix up header. Fix up template syntax.
sim/serialize.cc:
Include errno.h.
sim/startup.cc:
Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead
to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar
to this and may need changing in the future.
sim/syscall_emul.hh:
Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient.
sim/universe.cc:
Include errno.h
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base/traceflags.py:
Merge extra new CPU flags
cpu/static_inst.hh:
Include all the execute functions in static_inst_impl.hh
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base/traceflags.py:
Add new commit rate trace flag.
build/SConstruct:
Add extra option for efence.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Use function calls instead of direct indexing (avoids confusion).
cpu/beta_cpu/commit_impl.hh:
Add commit rate trace output (might not be worthwhile in the future).
cpu/beta_cpu/decode_impl.hh:
Remove some older hacks. Fix it so that the isntruction properly sets its next
PC to the one calculated by the branch.
cpu/beta_cpu/fetch_impl.hh:
Remove old commented code.
cpu/beta_cpu/iew_impl.hh:
Add extra check to ensure that the instruction is valid.
cpu/beta_cpu/regfile.hh:
Include trace file.
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No multiple requests to the same block outstanding from the same tester
Using false sharing, each tester only access a single byte within the block based on which tester it is
Allow more cycles before signalling deadlock, with do_events it may take some time with NACK/retry and many proccessors
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Changed SimpleCPU to not due functional access until the cache returns
Updated config file to use a simple cpu for second cpu in dual mode.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
Update cache completion event to perform the functional read upon completion
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean
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every time the committed PC changes from one symbol scope
to another.
Set function_trace=y on target CPU to enable.
To defer start, use function_trace_start=<tick>
(in addition to setting function_trace=y).
cpu/base_cpu.cc:
cpu/base_cpu.hh:
Add simple function-tracing support.
cpu/simple_cpu/simple_cpu.cc:
Add function_trace, function_trace_start params
Call traceFunctions() on instruction completion
cpu/simple_cpu/simple_cpu.hh:
Add function_trace, function_trace_start params
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base/loader/symtab.cc:
base/loader/symtab.hh:
Get rid of old unused calls.
cpu/simple_cpu/simple_cpu.hh:
No need to include base/loader/symtab.hh
kern/linux/linux_system.cc:
kern/tru64/tru64_system.cc:
Include base/loader/symtab.hh (since it's no longer included in system.hh)
sim/system.hh:
Replace include of base/loader/symtab.hh with forward class decl.
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cpu/exetrace.cc:
Fix dumb mistake.
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Simple text list of symbol (or address) and count
will be dumped to m5prof.<cpu-name> if the cpu's
pc_sample_interval param is set.
SConscript:
Add cpu/full_cpu/pc_sample_profile.cc
base/callback.hh:
Add a comment about MakeCallback.
Fix type in another comment.
base/loader/symtab.cc:
Revamp findNearestSymbol() to provide addresses of both
nearest symbols (preceding and following) as well as
string for former.
Move global definition of debugSymbolTable here too.
base/loader/symtab.hh:
Revamp findNearestSymbol() to provide addresses of both
nearest symbols (preceding and following) as well as
string for former.
Move global declaration of debugSymbolTable here too.
cpu/exetrace.cc:
Use new findNearestSymbol() interface for trace symbols.
kern/linux/linux_system.cc:
sim/system.cc:
Remove extern of debugSymbolTable (now in symtab.hh)
sim/process.cc:
Initialize debugSymbolTable if binary has a symbol table.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean
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all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
deal with changes in ev5.hh
arch/alpha/ev5.hh:
Macros are nasty, so let's get rid of them. Convert all
all macros to inline functions or constant typed variables.
Make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/isa_traits.hh:
move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
deal with isa addition
cpu/exec_context.hh:
be less isa specific and use the isa traits to figure out
what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
deal with changes in ev5.hh
I don't believe this masking is actually necessary. We should
look at removing it later.
dev/ide_ctrl.cc:
sort #includes
deal with changes in ev5.hh
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caches.
This added a snoopResponse callback to the caches, and a NACK to requests.
cpu/memtest/memtest.cc:
Modified to work with do_events:
No multiple requests to the same block outstanding at the same time from the same tester
Using false sharing, each tester does only 1 byte access using it's id as the blk offset
Allow for cycles before signaling deadlock, with do events it can take time to complete (NACK/blocked bus)
cpu/memtest/memtest.hh:
Updated to keep an id with each tester (used for address generation)
Updated to keep a list of outstanding address to prevent multiple outstanding per tester
//Should really look into doing store forwarding within the tester, then we can test more functionality
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checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.
arch/alpha/ev5.cc:
XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.
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deferral
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cpu/trace/opt_cpu.cc:
cpu/trace/trace_cpu.cc:
we don't want to register this cpu since it's not a real cpu
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the registration stuff all moves into BaseCPU
cpu/base_cpu.cc:
Move the registration stuff into the BaseCPU since all
other CPUs use it.
cpu/base_cpu.hh:
Move the defer registration stuff into the BaseCPU since all
other CPUs use it.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
registration stuff moved to base class
sim/system.cc:
the activation of exec contexts should happen at startup, not
when they are registered.
sim/system.hh:
the system now has a startup function
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SConscript:
arch/isa_parser.py:
cpu/static_inst.hh:
Add inorderCPU
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arch/alpha/isa_traits.hh:
Move defines to non full system code section so they can
be used elsewhere
cpu/simple_cpu/simple_cpu.cc:
Don't use magic numbers
cpu/simple_cpu/simple_cpu.hh:
simple format nit
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branch prediction, and makes memory dependence work properly.
SConscript:
Added return address stack, tournament predictor.
cpu/base_cpu.cc:
Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Register stats.
cpu/beta_cpu/alpha_params.hh:
Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
Removed one class.
cpu/beta_cpu/bpred_unit.hh:
Add in RAS, stats. Changed branch predictor unit functionality
so that it holds a history of past branches so it can update, and also
hold a proper history of the RAS so it can be restored on branch
mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
Added in stats, history of branches, RAS. Now bpred unit actually
modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
Add in sanity checks.
cpu/beta_cpu/comm.hh:
Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
Add in stats.
cpu/beta_cpu/commit_impl.hh:
Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
Stats.
cpu/beta_cpu/fetch.hh:
Stats, change squash so it can handle squashes from decode differently
than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
Add in stats. Change how a cache line is fetched. Update to work with
caches. Also have separate functions for different behavior if squash
is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
Added function to remove instructions from back of instruction list
until a certain sequence number.
cpu/beta_cpu/iew.hh:
Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
Debug stuff
cpu/beta_cpu/inst_queue.hh:
Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
Stats, change how mem dep unit works, debug stuff. Also add in
parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
Add in stats, change how memory dependence unit works. It now holds
the memory instructions that are waiting for their memory dependences
to resolve. It provides which instructions are ready directly to the
IQ.
cpu/beta_cpu/regfile.hh:
Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
Add in debugging statements.
cpu/beta_cpu/store_set.hh:
Reorder function arguments to match the rest of the calls.
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cpu/simple_cpu/simple_cpu.cc:
Send Copy
cpu/trace/opt_cpu.cc:
Calculate the block size correctly. Set lookupTable value directly, since the old way only worked for FA caches.
cpu/trace/trace_cpu.cc:
Don't start events if the hierarchy is in non-event mode.
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cpu/trace/opt_cpu.cc:
Change printout to look more like real stats, should really just make these stats someday.
--HG--
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associative simulation.
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
Add the ability to simulate less than fully-associative opt caches.
cpu/trace/reader/itx_reader.cc:
Add writeback to the command list.
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SConscript:
Add opt_cpu
cpu/simple_cpu/simple_cpu.cc:
Fix page spanning copy warning.
cpu/trace/reader/itx_reader.cc:
Fix reader to return correct address.
--HG--
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Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
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arch/alpha/isa_desc:
whitespace fix.
cpu/simple_cpu/simple_cpu.cc:
Add support to make sure we don't get alignment faults in copies. Warn if we go over an 8k page boundary.
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always build with dynamic libraries for mysqlclient
SConscript:
always use dynamic library now
cpu/pc_event.hh:
cleared lower 2 bits, since everything must be 4byte aligned
--HG--
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cpu/pc_event.cc:
mask off lower three bits so we can have an event in palcode
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arch/alpha/ev5.cc:
set the mode explictly rather than having a bool user/notuser
cpu/simple_cpu/simple_cpu.hh:
there is no class Kernel
kern/kernel_stats.cc:
use cpu_mode_num
kern/kernel_stats.hh:
add interrupt mode and use cpu_mode_num rather than constant
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
add events to change the mode to/from interrupt
sim/system.cc:
sim/system.hh:
add a pal symbol table
--HG--
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SConscript:
Add build support for ITX trace writer
cpu/trace/reader/itx_reader.cc:
Handle full 36 bit physical addressses.
cpu/trace/reader/itx_reader.hh:
Need a string header file here
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
Modify trace CPU to take a single trace and drive an instruction and data interfaces.
--HG--
extra : convert_revision : 4c81f2f9d9341df41f0ae45e4bda49800a43977c
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caches.
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
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single place so it's easier to work with.
- Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
- KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
- Factor common code out of LinuxSystem and Tru64System and put
it into the System base class. While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.
SConscript:
Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
kernelStats is now a pointer
the parameters to the system have been moved into their own
struct
base/trace.hh:
provide a little functor class for wrapping a string that
can allow you to define name() in any scope very simply
for use with DPRINTF
cpu/base_cpu.cc:
New order of arguments for consistency.
cpu/exec_context.cc:
kernelStats no longer has the level of indirection in it,
execContext has the indirection now. so, kernelStats is a pointer.
We also need a pointer to the kernelBinning stuff from the system
and we need to figure out if we want to do binning or not.
Move a whole bunch of code into kern_binning.cc so it's all
in the same place.
cpu/exec_context.hh:
We want pointers to the kernel binning/stats stuff and we'll
have the exec_context and system have the level of indirection
instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
call through the exec context to do the special binning
stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
Re-organize the stats stuff and remove the level of indirection
(that was there to simplify building) and move the binning stuff
into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
move lots of common system code into the base system class so
that it can be shared between linux, tru64, and whatever else
we decide to support in the future.
Make the constructor take a pointer to a parameter struct so that
it is easier to pass parameters to the parent.
kern/system_events.cc:
move the majority of the binning code into the Kernel::Binning class
in the kern_binning file
kern/system_events.hh:
FnEvents only need to know the bin
create the Idle start event to find the PCBB of the idle
process when it starts.
kern/tru64/tru64_events.cc:
memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
re-order args for consistency
--HG--
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Put correct date in copyright headers based on bk changesets
LICENSE:
Updated copyright on license file
README:
Updaded readme to reflect shift to scons and linux support
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
updated copyright (only changeset in 2004)
kern/kernel_stats.cc:
kern/kernel_stats.hh:
updated copyright
--HG--
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to do multiple instructions per cycle.
--HG--
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cpu/trace/reader/m5_reader.cc:
Wrap assert variable in NDEBUG
--HG--
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--HG--
extra : convert_revision : 0bd6506e79600775dd0f72996120321f249b3411
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address can be zero for a copy
--HG--
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arch/alpha/ev5.cc:
cpu/simple_cpu/simple_cpu.cc:
update for new event interface
base/stats/events.cc:
implement the ignore event function which matches sim objects from which
to ignore events.
Make insert event like insert data and make it able to insert many
events in a single transaction with the database.
base/stats/events.hh:
Make it possible to ignore events
sim/sim_object.cc:
make recordEvent a member function of SimObject to implement
the ignore function easily
sim/sim_object.hh:
implement the ignore event stuff in the sim object. This is a
bit of a hack, but an easy place to put it.
--HG--
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--HG--
extra : convert_revision : d4938c6011173d3017f47fd592c4b5e4c8d543a3
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--HG--
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