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2005-06-05Update #defines for the O3CPU. Also include the copyright.Kevin Lim
base/timebuf.hh: Updated copyright. cpu/o3/2bit_local_pred.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/btb.hh: cpu/o3/comm.hh: cpu/o3/commit.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/cpu_policy.hh: cpu/o3/decode.hh: cpu/o3/fetch.hh: cpu/o3/free_list.hh: cpu/o3/iew.hh: cpu/o3/inst_queue.hh: cpu/o3/mem_dep_unit.hh: cpu/o3/ras.hh: cpu/o3/regfile.hh: cpu/o3/rename.hh: cpu/o3/rename_map.hh: cpu/o3/rob.cc: cpu/o3/rob.hh: cpu/o3/rob_impl.hh: cpu/o3/sat_counter.hh: cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Updated #define to have correct path. docs/footer.html: Remove e-mail addr. --HG-- extra : convert_revision : 68d7af52674621dc3b6d6ac0d564790ffd595fe3
2005-06-05Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into crampon.my.domain:/z/binkertn/research/m5/head --HG-- extra : convert_revision : d46f23e63e4a8c6325bcdeaf6cdd76b9e6208707
2005-06-05Change SamplingCPU to Sampler.Steve Reinhardt
--HG-- extra : convert_revision : ddba327a572804954adcebfff1182b97d474c020
2005-06-05move eio stuff to encumberedNathan Binkert
--HG-- extra : convert_revision : 9061382dba285c84931f8825e7159db0e9899944
2005-06-04shuffle files around for new directory structureNathan Binkert
--HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04more portableNathan Binkert
arch/alpha/alpha_tru64_process.cc: Sort #includes Make code more portable. g++ doesn't seem to always like struct ::stat (and others). So, we typedef stat outside of the namespace as something else and use the typedef base/hostinfo.cc: use snprintf to quell warning base/inifile.cc: use strncpy to quell warning base/stats/events.cc: don't use strcpy cpu/beta_cpu/btb.cc: use FloorLog2 instead of log2 cpu/beta_cpu/comm.hh: cpu/beta_cpu/inst_queue.hh: cpu/beta_cpu/sat_counter.hh: use sim/host.hh instead of stdint.h --HG-- extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
2005-06-01Rename sim/universe.{cc,hh} to root.{cc,hh} (since theSteve Reinhardt
object defined there was renamed Root long ago). SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: base/misc.cc: base/pollevent.cc: base/pollevent.hh: base/stats/events.cc: base/trace.hh: cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/inst_queue_impl.hh: cpu/pc_event.cc: cpu/static_inst.cc: dev/etherbus.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ide_disk.cc: dev/pcidev.cc: sim/builder.cc: sim/eventq.cc: sim/main.cc: sim/root.cc: sim/stat_control.cc: Rename sim/universe.{cc,hh} to root.{cc,hh}. --HG-- rename : sim/universe.cc => sim/root.cc extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-01Standardize clock parameter names to 'clock'.Steve Reinhardt
Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-05-26Added copyright.Kevin Lim
--HG-- extra : convert_revision : f6d53ac5130ea9f77f39f7c1aa35eeb1d5107599
2005-05-24Little debugging things.Steve Reinhardt
cpu/base_cpu.cc: Get rid of leftover debugging code. --HG-- extra : convert_revision : b33b2279499456b12a6242a9472ea5be724b37be
2005-05-20Minor changes to get new cpu to compile with FULL_SYSTEM.Steve Reinhardt
cpu/beta_cpu/full_cpu.hh: Make cpu_id protected rather than private so derived classes can access it. cpu/beta_cpu/regfile.hh: Get rid of troublesome debugging statement. --HG-- extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5
2005-05-19Fix up code for initial release. The main bug that remains is properly ↵Kevin Lim
forwarding data from stores to loads, specifically when they are of differing sizes. cpu/base_dyn_inst.cc: Remove unused commented out code. cpu/base_dyn_inst.hh: Fix up comments. cpu/beta_cpu/2bit_local_pred.cc: Reorder code to match header file. cpu/beta_cpu/2bit_local_pred.hh: Update comments. cpu/beta_cpu/alpha_dyn_inst.hh: Remove useless comments. cpu/beta_cpu/alpha_dyn_inst_impl.hh: cpu/beta_cpu/alpha_full_cpu_impl.hh: cpu/beta_cpu/comm.hh: cpu/beta_cpu/iew_impl.hh: Remove unused commented code. cpu/beta_cpu/alpha_full_cpu.hh: Remove obsolete comment. cpu/beta_cpu/alpha_impl.hh: cpu/beta_cpu/full_cpu.hh: Alphabetize includes. cpu/beta_cpu/bpred_unit.hh: Remove unused global history code. cpu/beta_cpu/btb.hh: cpu/beta_cpu/free_list.hh: Use full path in #defines. cpu/beta_cpu/commit.hh: cpu/beta_cpu/decode.hh: Reorder functions. cpu/beta_cpu/commit_impl.hh: Remove obsolete commented code. cpu/beta_cpu/fetch.hh: Remove obsolete comments. cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/rename_impl.hh: Remove commented code. cpu/beta_cpu/full_cpu.cc: Remove useless defines. cpu/beta_cpu/inst_queue.hh: Use full path for #defines. cpu/beta_cpu/inst_queue_impl.hh: Reorder functions to match header file. cpu/beta_cpu/mem_dep_unit.hh: Use full path name for #defines. cpu/beta_cpu/ras.hh: Use full path names for #defines. Remove mod operation. cpu/beta_cpu/regfile.hh: Remove unused commented code, fix up current comments. cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Update programming style. --HG-- extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
2005-05-03Large update of several parts of my code. The most notable change is the ↵Kevin Lim
inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-02Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-04-28Clean up output for pc break events, and remove a unneeded break event.Ron Dreslinski
cpu/pc_event.cc: Add a newline to the printout to clean up output kern/linux/linux_system.cc: Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts --HG-- extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
2005-04-14Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-11Make the notion of a global event tick independent of the actualNathan Binkert
CPU cycle ticks. This allows the user to have CPUs of different frequencies, and also allows frequencies and latencies that are not evenly divisible by the CPU frequency. For now, the CPU frequency is still set to the global frequency, but soon, we'll hopefully make the global frequency fixed at something like 1THz and set all other frequencies independently. arch/alpha/ev5.cc: The cycles counter is based on the current cpu cycle. cpu/base_cpu.cc: frequency isn't the cpu parameter anymore, cycleTime is. cpu/base_cpu.hh: frequency isn't the cpu parameter anymore, cycleTime is. create several public functions for getting the cpu frequency and the numbers of ticks for a given number of cycles, etc. cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/trace/trace_cpu.cc: Now that ticks aren't cpu cycles, fixup code to advance by the proper number of ticks. cpu/memtest/memtest.hh: cpu/trace/trace_cpu.hh: Provide a function to get the number of ticks for a given number of cycles. dev/alpha_console.cc: Update for changes in the way that frequencies and latencies are accessed. Move some stuff to init() dev/alpha_console.hh: Need a pointer to the system and the cpu to get the frequency so we can pass the info to the console code. dev/etherbus.cc: dev/etherbus.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ide_disk.hh: dev/ns_gige.cc: dev/ns_gige.hh: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. dev/ide_disk.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. Add some extra debugging printfs dev/platform.cc: dev/sinic.cc: dev/sinic.hh: outline the constructor and destructor dev/platform.hh: outline the constructor and destructor. don't keep track of the interrupt frequency. Only provide the accessor function. dev/tsunami.cc: dev/tsunami.hh: outline the constructor and destructor Don't set the interrupt frequency here. Get it from the actual device that does the interrupting. dev/tsunami_io.cc: dev/tsunami_io.hh: Make the interrupt interval a configuration parameter. (And convert the interval to the new latency/frequency stuff in the python) kern/linux/linux_system.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. kern/tru64/tru64_system.cc: For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. python/m5/config.py: Fix support for cycle_time relative latencies and frequencies. Add support for getting a NetworkBandwidth or a MemoryBandwidth. python/m5/objects/BaseCPU.mpy: All CPUs now have a cycle_time. The default is the global frequency, but it is now possible to set the global frequency to some large value (like 1THz) and set each CPU frequency independently. python/m5/objects/BaseCache.mpy: python/m5/objects/Ide.mpy: Make this a Latency parameter python/m5/objects/BaseSystem.mpy: We need to pass the boot CPU's frequency to the system python/m5/objects/Ethernet.mpy: Update parameter types to use latency and bandwidth types python/m5/objects/Platform.mpy: this frequency isn't needed. We get it from the clock interrupt. python/m5/objects/Tsunami.mpy: The clock generator should hold the frequency sim/eventq.hh: Need to remove this assertion because the writeback event queue is different from the CPU's event queue which can cause this assertion to fail. sim/process.cc: Fix comment. sim/system.hh: Struct member to hold the boot CPU's frequency. sim/universe.cc: remove unneeded variable. --HG-- extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-03-18Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : cbf8da2fe5c4155d9ed8318597d543ff105449d3
2005-03-15during a cache miss in the simple cpu we were finalizing the traceAli Saidi
data too early (before the cache miss completed) and therefore writing freeded memory after the cache miss completed. Also removed some spurious setAddr() and setData() calls. --HG-- extra : convert_revision : 3da82540c69c4c417aba3ed155e167d09431a1b2
2005-03-15Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 1391d03656a1d75809217c5b2e2aecca6f8a04ba
2005-03-15small cleanup to sampling cpu code.Nathan Binkert
cpu/base_cpu.cc: By default we should panic if the system doesn't explicitly support switchover. --HG-- extra : convert_revision : 4da2ec316d609cfb351fc5ceaa6d8fe36be14d4e
2005-03-10Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : a58535776cf5a3d17f8d9f65144cdf8db54289aa
2005-03-10Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : a5ee8e5187503203058da35ca44918f1ff7ae1eb
2005-03-09Changed all syscalls to use syscall return object.Ali Saidi
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: cpu/exec_context.hh: sim/process.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: Changed all syscalls to use syscall return object arch/alpha/isa_traits.hh: Added syscall return object that packages return value and return status into an object. sim/process.cc: renamed variable name to nm so base class function name() can be called --HG-- extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
2005-03-08Hand-merge static_inst.hh. These execute functions are within an external ↵Kevin Lim
file in the new CPU case. cpu/static_inst.hh: Hand-merge. These execute functions are within an external file in the new CPU case. --HG-- extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
2005-03-07Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : 2b73bffea88cb0e3bb5dff232a15afea8498f4e3
2005-03-01Add a new operation class for IPR accesses, and have IPR-accessingSteve Reinhardt
instructions use it (instead of IntALU, as before). Default config has a single non-pipelined 3-cycle unit. A bit conservative for the ev6 (some are 1, some are 3). arch/alpha/isa_desc: Make hw_mfpr and hw_mtpr use IprAccessOp op class. cpu/full_cpu/op_class.hh: Add IprAccess. --HG-- extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
2005-02-25Make all StaticInst methods const. StaticInst objects represent aSteve Reinhardt
particular binary machine instruction and should be immutable after they are constructed. cpu/simple_cpu/simple_cpu.hh: Make StaticInst parameters const. --HG-- extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
2005-02-25Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
2005-02-25Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.Kevin Lim
SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : e7d839327b07393bfcda0b77758b0832eaf1c1c0
2005-02-25Fix timing modeling of faults: functionally the very next instruction afterSteve Reinhardt
a faulting instruction is the fault handler, which appears as an independent instruction to the timing model. New code will stall fetch and not fetch the fault handler as long as there's a faulting instruction in the pipeline (i.e., the faulting inst has to commit first). Also fix Ali's bad-address assertion that doesn't apply to full system. Added some more debugging support in the process. Hopefully we'll move to the new cpu model soon and we won't need it anymore. arch/alpha/alpha_memory.cc: Reorganize lookup() so we can trace the result of the lookup as well. arch/alpha/isa_traits.hh: Add NoopMachInst (so we can insert them in the pipeline on ifetch faults). base/traceflags.py: Replace "Dispatch" flag with "Pipeline" (since I added similar DPRINTFs in other pipe stages). cpu/exetrace.cc: Change default for printing mis-speculated instructions to true (since that's often what we want, and right now you can't change it from the command line...). --HG-- extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
2005-02-22Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 8a558785c64b7c33e64523d3d887ea6e760c3d2b
2005-02-21Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : db688679bfd9c670ef44611de71640c3bf564fc0
2005-02-19Clean up CPU stuff and make it use params structsNathan Binkert
cpu/base_cpu.cc: cpu/base_cpu.hh: Convert the CPU stuff to use a params struct cpu/memtest/memtest.cc: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. Don't have any default parameters. cpu/memtest/memtest.hh: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. cpu/simple_cpu/simple_cpu.cc: Convert to use a params struct. remove default parameters cpu/simple_cpu/simple_cpu.hh: convert to use a params struct cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: this isn't really a cpu. don't derive from BaseCPU objects/MemTest.mpy: we only need one max_loads parameter sim/main.cc: Don't check for the number of CPUs since we may be doing something else going on. If we don't have anything to simulate, the simulator will exit anyway. --HG-- extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
2005-02-18Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : 8fb4bbf165b8c65a54db5fea18ec5aa95172a173
2005-02-17rename the simple cpu's multiplier parameter. call it width.Nathan Binkert
it makes more sense and is less confusing. cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: width is a better name than multiplier --HG-- extra : convert_revision : ea2fa4faa160f5657aece41df469bbc9f7244b21
2005-02-17Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : 88afcacc41f5b0fae0ed1ac1821b7ca88c407e85
2005-02-11Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 11832134b169aa827a1d03c96ef89edddf4b3dab
2005-02-11Fix up #defines to use full path; fix up code for g++ 3.4Kevin Lim
SConscript: Remove efence option from automatically being used. --HG-- extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69
2005-02-11Rework the command line paramters for python output and howNathan Binkert
output files and the output directory are are handled. Make the output directory configuration via a command line parameter, or an environment variable. SConscript: Add new output file stuff base/misc.cc: dev/simconsole.cc: use new output file code cpu/base_cpu.cc: use new output file code to generate output streams dev/etherdump.cc: use the output file code to find the output directory use a real stream instead of a pointer dev/etherdump.hh: use a real stream instead of a pointer objects/Root.mpy: output_dir and config_output_file are not longer configured here. sim/main.cc: - Completely rework the command line argument passing to deal with changes in python and output files. - Update help output to reflect changes. - Remove all direct support for .ini files. They are strictly for intermediate representation. - Remove the --foo:bar=blah syntax for .ini files and add --foo.bar=blah syntax for python. This will generate: foo.bar = 'blah' in the python script. - Add '-d' to set the output directory. - Use new output file code to access the output stream. sim/serialize.cc: use the new code to find the output directory sim/universe.cc: Get rid of makeOutputStream. Use the new output file code. Remove output_dir and config_output_file as parameters. --HG-- extra : convert_revision : df2f0e13d401c3a60cae1239aa1ec3511721544d
2005-02-09MergerRon Dreslinski
cpu/simple_cpu/simple_cpu.hh: Merge --HG-- extra : convert_revision : 1b6003ac731051fefacb7d7a30c317553b4bf1bc
2005-02-09Some more useful debugging info for kernel panic and die eventsRon Dreslinski
Increase the default number of CSHR's, we should really fix this or make it a parameter Use a setBlocked call to tell the bus it should block New technique for sampling and switchover: 1) Sampler switchover event happens 2) All cpus in the current phase of sampling associated with this sampler are signaled to switchover 3) Each cpu drains it's pipe of things being executed (stops fetching and waits for empty pipe) 4) Once the pipe is empty the cpu calls back to the sampler to signal it has finished, and moves into the switchedout state (continues not to fetch) 5) The sampler collects all the signals, once all cpus are drained it calls the new cpu's in the next phase to takeover from the correct cpu 6) The statistics are reset and the next switchover time is calculated from this point cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: Reconfigure the way the sampling switchover works cpu/pc_event.cc: More debugging information on kernel panic's kern/linux/linux_system.cc: More debug info for Kernel Die events kern/linux/linux_system.hh: More debug info for kernel die events --HG-- extra : convert_revision : 61cc42e43ba738705aa1f1d167b65d4d6dee51ae
2005-02-04Hand mergeKevin Lim
--HG-- extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
2005-02-03Add support for CPU models to execute the effectiveSteve Reinhardt
address calculation and memory access portions separately. Not currently used by any CPU models, but Kevin says he needs this. Also clean up handling of execution tracing for memory accesses (move it all into isa_desc and out of CPU models). Got rid of some ancient unused code too. arch/alpha/isa_desc: Add execute() methods to EAComp and MemAcc portions of memory access instructions, to allow CPU models to execute the effective address calculation and memory access portions separately. Requires the execution context to remember the effective address across the two invocations. Added setEA() and getEA() methods to execution context to support this. A model that does not use the split execution model can panic if these methods are called. Also added hook to call traceData->setAddr() after EA computation on any load or store operation. arch/isa_parser.py: Call traceData->setData() on memory writes (stores). cpu/simple_cpu/simple_cpu.cc: Get rid of unused code. cpu/simple_cpu/simple_cpu.hh: Add (non-functional) setEA() and getEA() methods for new split memory access execution support. --HG-- extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
2005-01-18Move trace data function to .cc file.Kevin Lim
--HG-- extra : convert_revision : 8180068747489978a2bbaa096dc73b0cfd14b052
2005-01-14Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most ↵Kevin Lim
changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-11Merge changes.Kevin Lim
base/traceflags.py: Merge extra new CPU flags cpu/static_inst.hh: Include all the execute functions in static_inst_impl.hh --HG-- extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
2005-01-11Slight fixes, add in commit trace flag.Kevin Lim
base/traceflags.py: Add new commit rate trace flag. build/SConstruct: Add extra option for efence. cpu/beta_cpu/alpha_full_cpu_impl.hh: Use function calls instead of direct indexing (avoids confusion). cpu/beta_cpu/commit_impl.hh: Add commit rate trace output (might not be worthwhile in the future). cpu/beta_cpu/decode_impl.hh: Remove some older hacks. Fix it so that the isntruction properly sets its next PC to the one calculated by the branch. cpu/beta_cpu/fetch_impl.hh: Remove old commented code. cpu/beta_cpu/iew_impl.hh: Add extra check to ensure that the instruction is valid. cpu/beta_cpu/regfile.hh: Include trace file. --HG-- extra : convert_revision : 4ee1dc88f8a5ed9b65486c6c111a3718a8040e42
2004-12-14Modified to work with do_eventsRon Dreslinski
No multiple requests to the same block outstanding from the same tester Using false sharing, each tester only access a single byte within the block based on which tester it is Allow more cycles before signalling deadlock, with do_events it may take some time with NACK/retry and many proccessors --HG-- extra : convert_revision : 4c8eab99082c53840a5ad2a926457dfc27f23b77