gem5 - gem5

Age	Commit message (Expand)	Author
2004-07-12	make the cache access latency a parameter that is based on bus	Nathan Binkert
2004-06-26	rewrote uart and renamed console.cc to simconsole to reduce confusion	Ali Saidi
2004-06-10	Fixes for detailed boot, made cttz and ctlz instructions more compact,	Ali Saidi
2004-06-04	Updated copyright on Tsunami and kern/linux files.	Ali Saidi
2004-02-20	Fix the RTC code so it is in the cchip, only interrupt processors that	Ron Dreslinski
2004-02-20	Add support for IPI's and extend RTC to interrupt all Processors	Ron Dreslinski
2004-02-16	1 << x != (uint64_t)1 << x	Ali Saidi
2004-02-16	Changed device IRQ back to 1	Andrew Schultz
2004-02-16	Added new aic register definition, fix some interrupt related calls	Andrew Schultz
2004-02-15	Rewrote interrupt code to handle masking correctly and changed every	Ali Saidi
2004-02-11	Merge	Ali Saidi
2004-02-11	added serializeation code	Ali Saidi
2004-02-10	Fix masking of read/write address to get read/write offset	Andrew Schultz
2004-02-10	Changed new linux stuff to work with new FunctionalMemory interface and	Andrew Schultz
2004-02-05	added some comments	Ali Saidi
2004-02-03	Fix to support redefinition of functional_memory base class	Andrew Schultz
2004-01-30	Linux boots with no devices	Ali Saidi
2004-01-28	moved devices around in config space and support figuring out cpuid	Ali Saidi
2004-01-28	Add support for PIC interrupts in IO, and DIRx interrupts in CChip	Ron Dreslinski
2004-01-28	our first interrupt	Ali Saidi
2004-01-27	Add support for RTC to interrupt, HACK in alpha_console temporary	Ron Dreslinski
2004-01-21	one step closer to booting	Ali Saidi
2004-01-15	Slowly on our way to booting with Tsunami	Ali Saidi