| Age | Commit message (Collapse) | Author |
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add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation
SConscript:
build/SConstruct:
always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
Add a way to read the DRIR for validation.
--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
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dev/tsunami_cchip.cc:
add a fake register to tsunami that we can do 32bit reads to.
Warn on access.
--HG--
extra : convert_revision : d87860f3b527528151c23431556039bca6e12945
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wierd ini files. The ini files are still used as an intermediate step,
but a sophisticated python library exists to help build them more
easily.
SConscript:
add the new embedded file stuff
remove all of the old object description junk
base/inifile.cc:
base/inifile.hh:
get rid of findDefault and findAppend since they were the source
of much evil.
base/trace.cc:
For now, if we don't have the dprintf_stream set up, dump
to standard out. We probably want a command line option
for this.
dev/alpha_console.cc:
PioDevice now takes a platform parameter.
All PioDevices must have a pio_latency parameter. We stick
a dummy parameter in here for now until we get rid of the
builder stuff.
dev/alpha_console.hh:
don't need Platform anymore
dev/baddev.cc:
PioDevice now takes a platform parameter.
All PioDevices must have a pio_latency parameter. We stick
a dummy parameter in here for now until we get rid of the
builder stuff. Same for the platform parameter, though we just
pass the PioDevice a null parameter since it isn't used by
this device and it's quicker.
dev/baddev.hh:
fix #include guards
dev/etherlink.cc:
rename parameters.
dev/ethertap.cc:
rename parameters
dev/ide_ctrl.cc:
All devices need an address even if it will get overwritten later.
dev/ide_disk.cc:
use an enum for the drive ID stuff.
rename disk_delay -> delay
Actually, I think that we should implement "cable select" and
have the controller tell the drive what it is.
dev/io_device.cc:
dev/io_device.hh:
All IO devices take a Platform *
dev/ns_gige.cc:
all devices need an io_bus. rename header_bus to io_bus
We don't need stuff for the interrupt controller since
it's all in the platform now.
dev/ns_gige.hh:
We don't need stuff for the interrupt controller now since
it's all in the platform.
dev/pciconfigall.cc:
Pass a dummy NULL to the PioDevice for the platform since
we don't need one.
dev/pcidev.cc:
Move a bunch of common functionality into the PciDev
dev/platform.hh:
remove unneeded code
dev/tsunami.cc:
remove unused param
dev/tsunami_cchip.cc:
pass platform pointer
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
pass platform variable
dev/uart.hh:
don't need to keep a platform pointer. it's in the base class
kern/linux/linux_system.cc:
kern/tru64/tru64_system.cc:
rename some parameters
sim/builder.cc:
clean up builder code. use more parameters from the
config node. all sections with a type= are now created,
the old mechanisms no longer work
sim/builder.hh:
remove some extra variables since they are found in the ConfigNode
sim/main.cc:
add a quick hack command line argument -X to dump out the
embedded files. (probably should be fixed up a little.)
accept .mpy files
printing to the streams has to happen after the hierarchy
is built since we're moving away from param contexts
sim/param.cc:
add parsing support for ranges
sim/process.cc:
isValid isn't very useful anymore. interpret the names
stdout, stderr, cout, cerr for the file descriptors
sim/pyconfig/SConscript:
Add Action handlers for creating an embedded python file
and for creating an embedded C file.
use these action handlers to embed all objects found in the objects
tree into the binary along with the importer and the m5config stuff
sim/pyconfig/m5config.py:
Major changes to the original configuration file generator. These
changes largely involve implementing copy-on-write like semantics
for all of the SimObjects. Real documentation must be written.
sim/universe.cc:
Universe becomes a SimObject since we don't really have the notion of
param contexts in the python code.
--HG--
rename : sim/pyconfig/m5configbase.py => sim/pyconfig/m5config.py
extra : convert_revision : c353453e5beb91c37f15755998fc0d8858c6829a
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base/socket.cc:
Make panic print a more worthwhile message
dev/tsunami.hh:
Change max number of tsunami cpus to be 64
dev/tsunamireg.h:
Add new registers and register blocks for 64 cpu tsunami
--HG--
extra : convert_revision : 3ceaaa998518ded8613bc64edc04cb9120fd3d15
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all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
deal with changes in ev5.hh
arch/alpha/ev5.hh:
Macros are nasty, so let's get rid of them. Convert all
all macros to inline functions or constant typed variables.
Make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/isa_traits.hh:
move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
deal with isa addition
cpu/exec_context.hh:
be less isa specific and use the isa traits to figure out
what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
deal with changes in ev5.hh
I don't believe this masking is actually necessary. We should
look at removing it later.
dev/ide_ctrl.cc:
sort #includes
deal with changes in ev5.hh
--HG--
extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
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never clear about whether the end of the range was inclusive
or exclusive. Make it inclusive, but also provide a RangeSize()
function that will generate a Range based on a start and a size.
This, in combination with using the comparison operators, makes
almost all usages of the range not care how it is stored.
base/range.cc:
Make the end of the range inclusive.
start/end -> first/last
(end seems too much like end() in stl)
base/range.hh:
Make the end of the range inclusive.
Fix all comparison operators so that they work correctly with
an inclusive range. Also, when comparing one range to another
with <, <=, >, >=, we only look at the beginning of the range
beacuse x <= y should be the same as x < y || x == y. (This wasn't
the case before.)
Add a few functions for making a range:
RangeSize is start and size
RangeEx is start and end where end is exclusive
RangeIn is start and end where end is inclusive
start/end -> first/last
(end seems too much like end() in stl)
dev/alpha_console.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
Use the RangeSize function to create a range.
--HG--
extra : convert_revision : 29a7eb7fce745680f1c77fefff456c2144bc3994
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dev/tsunami_cchip.cc:
updates to ipi handling chipset code
sim/system.cc:
debugSymbolTable, now has symbols from pal, console, and linux
--HG--
extra : convert_revision : c981d857f7e3d75f4c46172809e6d14e5f0a1238
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ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
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base/traceflags.py:
removed TsunamiUart/TlaserUart and added a plain Uart
dev/alpha_console.cc:
updated for new simconsole
dev/platform.hh:
added a uart member to platform
dev/simconsole.cc:
dev/simconsole.hh:
removed lots of legacy code, it should all be ours now.
converted tabs to 8 spaces
added our copyright
dev/tsunami.cc:
uses simconsole.hh rather than console.hh
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
never needed console.hh
dev/tsunami_io.hh:
this does need eventq.hh and it just happend to be working whenn console.hh was
included everywhere
dev/tsunamireg.h:
added a couple more 8250/16550 uart defines
dev/uart.cc:
new uart code, rewritten to support both tlaser and tsunami (both a 8250 and 8530
uart).
dev/uart.hh:
updated for new uart, legacy code removed
--HG--
rename : dev/console.cc => dev/simconsole.cc
rename : dev/console.hh => dev/simconsole.hh
rename : dev/tsunami_uart.cc => dev/uart.cc
rename : dev/tsunami_uart.hh => dev/uart.hh
extra : convert_revision : e663352d49d4c2d3c95643030cf73c0e85ba2f08
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and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
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dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
Updated copyright
dev/tsunamireg.h:
Updated copyright and fixed a ULL
--HG--
extra : convert_revision : 4800bd227c7064044ee98169d6a91f74c791956f
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are present
dev/tsunami_cchip.cc:
Only need to interrupt processors that are there
Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
Make a call to the RTC interrupt routine instead
--HG--
extra : convert_revision : 88113664d0e54a7dddc00ec11ff9b9d088232b31
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dev/tsunami_cchip.cc:
Add support for IPI, making changes to read/write to MISC register
Particularly the IPREQ, IPINTR, and ITINTR subfields
dev/tsunami_cchip.hh:
Make an array to keep track of the number of outstanding IPI's,
Extend RTC to interrupt all processors, not just cpu0
dev/tsunami_io.cc:
Extend RTC to interrupt all present proccessors, not just cpu0
--HG--
extra : convert_revision : 0715cbf0abb06002c0fb0b05ef369304cdf75001
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dev/tsunami_cchip.cc:
fixed another problem with the interrupt code, should all work now
--HG--
extra : convert_revision : 1d9fe6081b6391e3e09f1c4a9380a30240fac6dc
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--HG--
extra : convert_revision : 3fb611e6e0305fe9854cdf7813492b75750cd7a9
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dev/tsunami_cchip.cc:
Change interrupt level to 20 for devices
--HG--
extra : convert_revision : deee68d5434643dc751de08e5a804c14d1a86efd
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interrupt to use a different subnumber since both devices could
interrupt at the same time and we don't want to loose one.
dev/tsunami_cchip.cc:
rewrote interrupt code to handle interrupt mask clearing correctly
dev/tsunami_cchip.hh:
changed (post/clear)DRIR to use a interrupt number rather than a vecotr
dev/tsunami_io.cc:
updated for new post/clearDRIR calls
--HG--
extra : convert_revision : 5b39f5e15a66d5eb6e689e6ece62f99b5fa735ab
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dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/tsunami_uart.cc:
SCCS merged
--HG--
extra : convert_revision : da3d1998d6dd39e0d3f8754074c513cdd8a4193c
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--HG--
extra : convert_revision : 468f3c739707d167af43562695b604fd7dead661
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Changed base_linux.ini file to use physical addresses
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Fix masking of read/write address to get read/write offset
dev/tsunami_uart.cc:
Fix masking of read/write address to get read/write offset
Also added add_child call that was missed
dev/tsunami_uart.hh:
Changed size to 0x8
--HG--
extra : convert_revision : 1468ca43167bfb28b28c4510401a1ebad683e102
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some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
--HG--
extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
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--HG--
extra : convert_revision : b33c94984f8d9ac2baf8d7b45fa79460846b1755
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--HG--
extra : convert_revision : c06b2cfd2787022ee5dc664886873a9afa459434
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dev/tsunami.hh:
Started commenting code
dev/tsunami_cchip.cc:
removed unneccessary config files
dev/tsunami_io.cc:
Added code to see the value written
dev/tsunami_uart.cc:
conviently one of the addresses the SuperI/O southbridge can be is the same space
as the UART. This stops the simulator from panicing although it should probably be
changed a bit.
--HG--
extra : convert_revision : a3334a2c418ee8228089d0e1791fa78bbb276fe5
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from cchip register
dev/tsunami_cchip.cc:
added support for figuring out which cpu you are
--HG--
extra : convert_revision : 7862678a259931bb0a5b2ca8ad298a704bd272ec
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dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
Add Interrupt capabilities for DIRx, added postDRIR and clearDRIR
functions
dev/tsunami_io.cc:
Add PIC interrupts, and post/clearPIC functions
dev/tsunami_io.hh:
Add support for PIC interrupts, added post/clearPIC functions
--HG--
extra : convert_revision : b705568670b157c1a4496c365226526fa96e21e0
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cpu/exetrace.cc:
added looking for symbols at PC+4 and PC+8 thanks to gcc skiping
setting the gp where it can and jumping <func>+8
dev/console.cc:
commented out weird interrupt per nate's suggestion
dev/tsunami_cchip.cc:
moved rtc flag to correct bit
dev/tsunami_io.cc:
time interrupt will be 1024Hz and at some point be configurable by
linux
dev/tsunami_io.hh:
Timer interrupt will be 1024hz for now and in the future be
configurable by linux
--HG--
extra : convert_revision : 2fcc924c8848eb3c6166d9d517617ed193a2b89a
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dev/alpha_console.cc:
Fix reference to tlaserclock, HACK FOR NOW
dev/alpha_console.hh:
fix reference to tlaser_clock, HACK FOR NOW
dev/tsunami.cc:
Add proper tsunami chip pointers
dev/tsunami.hh:
add proper tsunami chip pointers add RTC interrupt capabilities
dev/tsunami_cchip.cc:
Add proper Interrupt for RTC
dev/tsunami_cchip.hh:
Add proper interrupt for RTC
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make RTC interrupt
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
Add back pointer to tsunami
--HG--
extra : convert_revision : 2b0a8616b0bed8d9962ee5ca643dce56b9922d52
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dev/alpha_access.h:
removed my attempted hack to get console compling in linux
dev/tsunami.cc:
dev/tsunami.hh:
added pchip pointer to tsunami
dev/tsunami_cchip.cc:
made printing better
dev/tsunami_cchip.hh:
commented out back pointer for now, since the parser has issues with it
dev/tsunamireg.h:
added pchip registers
--HG--
extra : convert_revision : b4fceb7d08e757d9aaf37df8eb1bcd5ae29ce0da
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--HG--
extra : convert_revision : ec8e7e2dc929ad84c5e320fbfb02070e94cd1ad1
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