gem5 - gem5

Age	Commit message (Expand)	Author
2004-07-12	make the cache access latency a parameter that is based on bus	Nathan Binkert
2004-06-26	rewrote uart and renamed console.cc to simconsole to reduce confusion	Ali Saidi
2004-06-16	Updated serialization code and added #if tracing so that make fast	Ali Saidi
2004-06-10	Fixes for detailed boot, made cttz and ctlz instructions more compact,	Ali Saidi
2004-06-04	Updated copyright on Tsunami and kern/linux files.	Ali Saidi
2004-06-01	Removed dynamic cast to get interrupt frequency and replaced with a	Ali Saidi
2004-05-30	Cleaned up and commented code. I think we are ready to merge with head.	Ali Saidi
2004-02-10	Changed new linux stuff to work with new FunctionalMemory interface and	Andrew Schultz
2004-02-05	Now skips the calibrate_delay loop in the kernel boot	Andrew Schultz
2004-02-03	Fix to support redefinition of functional_memory base class	Andrew Schultz
2004-01-28	Add support for PIC interrupts in IO, and DIRx interrupts in CChip	Ron Dreslinski
2004-01-28	our first interrupt	Ali Saidi
2004-01-27	Add support for RTC to interrupt, HACK in alpha_console temporary	Ron Dreslinski
2004-01-26	Support for Tsunami coming along... RTC, PIC working, UART in progress	Ali Saidi
2004-01-23	Add RTC event for uip bit	Ron Dreslinski
2004-01-22	added the 8254 programmable interval timer	Ali Saidi
2004-01-22	renamed tsunami_dma to tsunami_io	Ali Saidi