gem5 - gem5

Age	Commit message (Expand)	Author
2004-07-12	make the cache access latency a parameter that is based on bus	Nathan Binkert
2004-06-10	Fixes for detailed boot, made cttz and ctlz instructions more compact,	Ali Saidi
2004-06-04	Merge	Ali Saidi
2004-06-04	Updated copyright on Tsunami and kern/linux files.	Ali Saidi
2004-06-03	Fixes in translation in PCI to DMA address to fix boot problems with	Andrew Schultz
2004-05-30	Cleaned up and commented code. I think we are ready to merge with head.	Ali Saidi
2004-05-11	Changes to fix bad DMA handling by disk when using scatter gather page	Andrew Schultz
2004-05-06	Whole mess'o'changes.. see individual files	Andrew Schultz
2004-02-21	Added initial (hackish) support for translating between a PCI bus address	Andrew Schultz
2004-02-11	Merge	Ali Saidi
2004-02-11	added serializeation code	Ali Saidi
2004-02-10	Fix masking of read/write address to get read/write offset	Andrew Schultz
2004-02-10	Changed new linux stuff to work with new FunctionalMemory interface and	Andrew Schultz
2004-02-03	Fix to support redefinition of functional_memory base class	Andrew Schultz
2004-01-27	Add support for RTC to interrupt, HACK in alpha_console temporary	Ron Dreslinski
2004-01-21	one step closer to booting	Ali Saidi