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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
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simple-object-demo
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uart.cc
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Author
2005-06-05
Many files:
Steve Reinhardt
2005-06-05
Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-clean
Ali Saidi
2005-06-05
split uart into urt8250 and uart8530
Ali Saidi
2005-06-04
shuffle files around for new directory structure
Nathan Binkert
2005-06-01
Standardize clock parameter names to 'clock'.
Steve Reinhardt
2005-03-29
expose variables for number of global events per simulated second,
Nathan Binkert
2005-01-15
New and improved configuration mechanism. No more writing of
Nathan Binkert
2004-11-13
Macros are nasty, so let's get rid of them. Convert all
Nathan Binkert
2004-10-22
Clean up the Range class and associated usages. The code was
Nathan Binkert
2004-10-16
Fixes for bigendian platforms
Ali Saidi
2004-07-14
Fix serialization when a tx interrupt isn't scheduled
Erik Hallnor
2004-07-12
make the cache access latency a parameter that is based on bus
Nathan Binkert
2004-06-29
Another fix for the too much work problem in 2.6. This should do it.
Ali Saidi
2004-06-28
With the new uart code 300 cycles isn't quite enough, 350 seems to
Ali Saidi
2004-06-26
rewrote uart and renamed console.cc to simconsole to reduce confusion
Ali Saidi