Age | Commit message (Collapse) | Author |
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Turbolaser)
base/range.hh:
Change semantics of range to be inclusive of the end value, may need to
check other users of range to make sure they are semantically correct.
This was needed for access of last byte in range of address on IDE and
makes sense for case of range from 0 to all f
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
Whole mess of changes.. at current state simulator will boot and read
partition table and then have a bunch of errors and panic
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/platform.hh:
Changes to work with platform separation
dev/tsunami.cc:
dev/tsunami.hh:
Change to work with platform separation
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assumes that all PCI devices are DmaDevices, and if not, they can just
ignore the DMA stuff)
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extra : convert_revision : aa58b658370696674ca4c32b265bc0400e5dda5a
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dev/pcidev.cc:
member variables should begin with lowercase so they don't get confused with types.
dev/pcidev.hh:
member variables must begin with lowercase so they don't get confused with types.
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extra : convert_revision : f083baa60d0fbf64d858d684ff70ee06e7b7765d
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sim object(depends on which platform tsunami/tlaser is being used)
dev/alpha_console.cc:
Use dynamice casting once during build to get at the proper device to calculate the frequency.
It is either a tsunami_IO or a tlaser_clock depending on platform (tsunami/tlaser).
If the simobject is not of either of those types then panic
dev/alpha_console.hh:
Pass in a SimObject * that is to either a tlaser_clock or a tsunami_IO
sim/sim_object.cc:
Make it so that you can have a SimObjectParam of type SimObject:
example:
SimObjectParam<SimObject *> so;
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extra : convert_revision : 08239ef23762b8ea11311630b73fe885d939402e
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scsi since we're not going that route anymore anyway. esp because it was giving me an error i couldn't seem to fix.
dev/alpha_console.cc:
missed this >>>> after i merged
kern/linux/linux_system.cc:
get rid of FS_MEASURES and change FnEvent to LinuxFnEvent
kern/linux/linux_system.hh:
get rid of FS_MEASURE
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so for consistency I changed it.
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami.hh:
change PCIConfigAll to PciConfigAll
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extra : convert_revision : d2fa3f59b906c870fd9d46cfa94728c7587e3652
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delay is more or less folded into the packet time, but an additional
delay is possible representing crossing a long haul link, or some
switches, etc.
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vary in size, so we're explicit about the fields.
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dev/alpha_console.cc:
setAddrRange -> addAddrRange
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fix serialization
dev/etherlink.cc:
fix serialization
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and a physical memory address for DMA
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
Changed registers to array and added mapping function to translate between
PCI bus space and physical address space
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extra : convert_revision : e9dc4de4e7effe8e8e2365298843d6f767b5a289
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of faking it. Renamed stuff to follow our style. Lots of
general cleanup.
dev/etherpkt.hh:
fix up includes
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are present
dev/tsunami_cchip.cc:
Only need to interrupt processors that are there
Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
Make a call to the RTC interrupt routine instead
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make it so that pio devices must respond with some delay.
dev/io_device.cc:
don't forget to include dma_interface.hh so we could use it.
dev/io_device.hh:
the generic BusInterface isn't enough for doing DMA
we need the actual DMAInterface
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dev/etherdump.cc:
now that init is automatically called by the framework, don't
init twice.
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extra : convert_revision : 16dcdef67aa193ed71ff546e7b255d60f39bf13d
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/memory
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extra : convert_revision : 691c89ebacb3c5a5eb67359ed102646b8547dd17
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dev/tsunami_cchip.cc:
Add support for IPI, making changes to read/write to MISC register
Particularly the IPREQ, IPINTR, and ITINTR subfields
dev/tsunami_cchip.hh:
Make an array to keep track of the number of outstanding IPI's,
Extend RTC to interrupt all processors, not just cpu0
dev/tsunami_io.cc:
Extend RTC to interrupt all present proccessors, not just cpu0
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and for link events
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dev/tsunami_cchip.cc:
fixed another problem with the interrupt code, should all work now
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dev/tsunami_cchip.cc:
Change interrupt level to 20 for devices
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dev/tsunami_cchip.cc:
SCCS merged
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interrupt to use a different subnumber since both devices could
interrupt at the same time and we don't want to loose one.
dev/tsunami_cchip.cc:
rewrote interrupt code to handle interrupt mask clearing correctly
dev/tsunami_cchip.hh:
changed (post/clear)DRIR to use a interrupt number rather than a vecotr
dev/tsunami_io.cc:
updated for new post/clearDRIR calls
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extra : convert_revision : 5b39f5e15a66d5eb6e689e6ece62f99b5fa735ab
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dev/tsunami_cchip.cc:
Changed to point to IPL 20 rather than 21
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arch/alpha/vtophys.cc:
base/remote_gdb.cc:
Fix to remote debugger while in PAL code
dev/pcidev.cc:
Remove extra debug printf
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In the future, this can be used for actual data, but for now, it's
so that devices can respond to timing accesses properly. This way,
an uncached access on a bus further away will take longer to respond.
dev/alpha_console.cc:
dev/alpha_console.hh:
suport the separate IO bus
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dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/tsunami_uart.cc:
SCCS merged
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Changed base_linux.ini file to use physical addresses
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Fix masking of read/write address to get read/write offset
dev/tsunami_uart.cc:
Fix masking of read/write address to get read/write offset
Also added add_child call that was missed
dev/tsunami_uart.hh:
Changed size to 0x8
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extra : convert_revision : 1468ca43167bfb28b28c4510401a1ebad683e102
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some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
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arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
Merge
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dev/tsunami.hh:
Added generic platform base class
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into zizzer.eecs.umich.edu:/y/saidi/work/m5
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dev/pcidev.cc:
Linux 2.6 writes the latency timer, so it was added to the list of
allowable writes
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
A couple of changes so that the new linux autoconf serial driver thinks
that the serial port exists and configures it
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extra : convert_revision : 6c026ef754e31de56c9b837ceb8f6be48c8d8d9c
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- Make the MemoryController use address ranges (via Range) instead
of an address and a mask
base/remote_gdb.cc:
reflect name change
dev/alpha_access.h:
better include
dev/alpha_console.cc:
- FunctionalMemory no longer takes care of mapping my address into
the proper address space. It must be done locally.
- the memory controller no longer uses a mask, but a size, and the
size is determined by the device, not the .ini file
- fix up address calculations to reflect the removal of a mask
- PhysicalMemory::getSize() -> PhysicalMemory::size()
dev/alpha_console.hh:
- FunctionalMemory no longer takes care of mapping my address into
the proper address space. It must be done locally.
- the memory controller no longer uses a mask, but a size, and the
size is determined by the device, not the .ini file
- fix up address calculations to reflect the removal of a mask
- get rid of MmapDevice and inherit from FunctionalMemory
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dev/tsunami.cc:
Changed so Tsunami has a pointer to the System to which it belongs.
Now it is derived from generic base class Platform so platform stuff
can be accessed based on the system
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Cleanup and added copyright
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
Added event to skip the "calibrate_delay" function, now calculate
loops_per_jiffy based on frequency, interrupt frequency, and constant
sim/system.hh:
Added pointer to generic Platform base class
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dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami.cc:
dev/tsunami.hh:
A bunch of changes to clean up new PCI code and to fix build
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execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
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dev/pcidev.cc:
dev/pcidev.hh:
BAR changes should now change the mmu mapping
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