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AgeCommit message (Expand)Author
2006-02-28Corrected some mistakes in the hand mergeGabe Black
2006-02-28Hand mergedGabe Black
2006-02-28Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
2006-02-27Changed targetarch to just arch.Gabe Black
2006-02-27MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather t...Gabe Black
2006-02-26add some support for random access of data in packet fifosNathan Binkert
2006-02-25Since the delayed write stuff is gone, get rid of regWriteNathan Binkert
2006-02-24Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
2006-02-24Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appr...Gabe Black
2006-02-23Merge zizzer:/bk/m5Ali Saidi
2006-02-23Get rid of the xc from the alphaAccess/alphaConsole backdoor device.Ali Saidi
2006-02-21Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old...Gabe Black
2006-02-21Made Addr a global typeGabe Black
2006-02-20Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
2006-02-20Finished the implementing the change of the ISA from a class to a namespaceGabe Black
2006-02-20Get rid of the code that delays PIO write accessesNathan Binkert
2006-02-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
2006-02-19Changes to untemplate StaticInst and StaticInstPtr, change the isa to a names...Gabe Black
2006-02-17Get rid of deque (poor memory allocation), switch them over to lists.Kevin Lim
2006-02-16Changed the fault enum into a class, and fixed everything up to work with it....Gabe Black
2006-02-12Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, ...Gabe Black
2006-02-03byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. T...Gabe Black
2005-11-28Virtualized SINIC fixesNathan Binkert
2005-11-25Virtualize sinicNathan Binkert
2005-11-25Add the capability to iterate through the packets in a pktfifo,Nathan Binkert
2005-11-22add the cpu number of the request to various panic and traceNathan Binkert
2005-11-21add support for delaying pio writes until the cache access occursNathan Binkert
2005-11-21have sinic use the new readBar/writeBar stuff that's in theNathan Binkert
2005-11-21Add a bunch of functions to manage the BAR addresses. ThisNathan Binkert
2005-11-20io_bus is split out into pio_bus and dma_bus so that any deviceNathan Binkert
2005-11-11Update random come to always have explict min/maxAli Saidi
2005-11-02Don't call Random.uniform() unnecessarilyAli Saidi
2005-11-02Merge zizzer:/bk/m5Ali Saidi
2005-11-02Add ability to slightly perturb latency of ethernet/memoryAli Saidi
2005-10-21Major changes to sinic device model. Rearrage read/write, betterNathan Binkert
2005-10-21missed another pio interface nameNathan Binkert
2005-10-21better naming for pio interfacesNathan Binkert
2005-10-21It's not necessary for a device to call recvDone, thatNathan Binkert
2005-10-18Shuffle around device names to make things easier to read.Nathan Binkert
2005-10-18use the dedicated flag, no more exposing the m5reg directlyNathan Binkert
2005-10-12better english in stat descriptions for NS GigENathan Binkert
2005-10-12Add support for 64-bit addresses to the NS GigE device model.Nathan Binkert
2005-09-29fix for delayed state machine changesAli Saidi
2005-09-24Fix IDE disk UDMA mode support mask to actually reflect support forSteve Reinhardt
2005-09-18Tweak the set of coalesced interruptsNathan Binkert
2005-09-17Fix the EtherDump parametersNathan Binkert
2005-09-12only set an approriately sized piece of data. so break where appropriateAli Saidi
2005-09-12fixes for gcc 4.0Ali Saidi
2005-08-23Lots of fixes to serialization and naming of various deviceNathan Binkert
2005-08-23don't use sprintf. It's not guaranteed to not scribble over memory.Nathan Binkert