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2006-02-28Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a
2006-02-27Changed targetarch to just arch.Gabe Black
SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
2006-02-27MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather ↵Gabe Black
than being created directly. arch/alpha/alpha_memory.cc: cpu/base_dyn_inst.cc: dev/alpha_console.cc: dev/pcidev.hh: dev/sinic.cc: MachineCheckFaults are now generated by the ISA, rather than being created directly. --HG-- extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
2006-02-26add some support for random access of data in packet fifosNathan Binkert
dev/pktfifo.cc: add support for copying arbitrary data out of a packet fifo dev/pktfifo.hh: add support for copying arbitrary data out of a packet fifo. Add functions to determine where in the fifo a particular packet is --HG-- extra : convert_revision : f8ddc994ce8577f29af0de3fa418a01e4e2cb0f1
2006-02-25Since the delayed write stuff is gone, get rid of regWriteNathan Binkert
and merge it with writeBar0 --HG-- extra : convert_revision : 354642e0d528b6a5a7f2cdf0264d93e738b2d4eb
2006-02-24Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch SConscript: arch/alpha/ev5.cc: dev/alpha_console.cc: Hand merged --HG-- extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2006-02-24Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where ↵Gabe Black
appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-23Merge zizzer:/bk/m5Ali Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.head cpu/simple/cpu.cc: remove initCPU from constructor dev/alpha_console.cc: we are panicing, so no need to return a fault --HG-- extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23Get rid of the xc from the alphaAccess/alphaConsole backdoor device.Ali Saidi
Now allocate an array of stacks indexed by cpu number which specify cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for their stacks before continuing. This change *REQUIRES* a the new console code to operate correctly. arch/alpha/ev5.cc: Add cpuId to initCPU/initIPR functions cpu/o3/cpu.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move the cpu initilization into an init() function since it now needs the CPU id which isn't known at construction dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: instead of the bootstrap variables, add space for 64 cpu stacks in the alpha access structure. sim/system.cc: start all cpus immediately rather than just the first one --HG-- extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-21Changed Fault * to Fault, which is a typedef to FaultBase *, which is the ↵Gabe Black
old Fault class renamed. --HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-21Made Addr a global typeGabe Black
--HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
2006-02-20Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : da72b3593037c2a67a56c799e292853b8aece907
2006-02-20Finished the implementing the change of the ISA from a class to a namespaceGabe Black
dev/sinic.cc: When DPRINTF disappears, reg32 becomes an unused variable. With -Werror, this causes the compile to fail. --HG-- extra : convert_revision : c003c714228491e060155070d192521c53d9e929
2006-02-20Get rid of the code that delays PIO write accessesNathan Binkert
until the cache access occurs. The fundamental problem is that a subsequent read that occurs functionally will get a functionally incorrect result that can break driver code. dev/ns_gige.cc: dev/ns_gige.hh: dev/sinic.cc: dev/sinic.hh: get rid of pio_delay write and the associated code to move the write to the cache access function dev/sinicreg.hh: no more write delays python/m5/objects/Ethernet.py: get rid of pio_delay write --HG-- extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
2006-02-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch arch/alpha/faults.hh: ur Using cleaned up fault class deiffinitions --HG-- extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19Changes to untemplate StaticInst and StaticInstPtr, change the isa to a ↵Gabe Black
namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-17Get rid of deque (poor memory allocation), switch them over to lists.Kevin Lim
Beware that using size() on a list is a O(n) operation. dev/ns_gige.hh: Remove typedefs that (I assume) were copied over from etherdev.hh. They were unused in the ns_gige code. --HG-- extra : convert_revision : 577954ec26b899bd6329ce6a4aaa1d9b0ba4f34c
2006-02-16Changed the fault enum into a class, and fixed everything up to work with ↵Gabe Black
it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-12Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, ↵Gabe Black
fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh. SConscript: Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh targetarch/isa_traits.hh is now included through arch/isa_traits.hh vptr.hh was removed from targetarch, and moved to sim arch/alpha/pseudo_inst.cc: Moved vptr.hh from targetarch to sim base/loader/object_file.hh: base/loader/symtab.hh: cpu/base.hh: dev/ide_disk.cc: Changed the include of isa_traits.hh from targetarch to arch cpu/static_inst.hh: dev/platform.hh: dev/simple_disk.hh: kern/tru64/dump_mbuf.cc: kern/tru64/mbuf.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/process.hh: sim/syscall_emul.hh: Changed the include of isa_traits.hh from targetarch to arch. kern/linux/linux_threadinfo.hh: Changed the include of vptr.hh from targetarch to sim. sim/byteswap.hh: Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t) sim/vptr.hh: Fixed the assert in the equals operator. Changed the AlphaISA namespace reference to TheISA. Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures. Added an include of arch/isa_traits.hh so that TheISA would be defined. --HG-- extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-03byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. ↵Gabe Black
The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: Added the endianness namespace. This may change. cpu/exec_context.hh: Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution. cpu/o3/alpha_cpu.hh: Forced LittleEndianness, for lack of a better solution. cpu/o3/alpha_cpu_impl.hh: Cleared away some commented out code. cpu/o3/fetch_impl.hh: Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution. cpu/simple/cpu.cc: Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine. dev/disk_image.cc: Changed the include path of byteswap.hh kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution. sim/system.cc: Forced LittleEndianness for lack of a better solution. --HG-- extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2005-11-28Virtualized SINIC fixesNathan Binkert
dev/pktfifo.hh: we can't modify i because it's used further down to remove the packet from the fifo. Instead, copy the iterator and modify that to get the previous packet. dev/sinic.cc: - don't change the transmit state and kick the machine unless we're at the head of the txList. - add a couple of debugging statements to figure out how far along we've gotten in processing a packet. - assert that the current tx vnic has something to do when we start processing the state machine. --HG-- extra : convert_revision : 588fe2c7d810be0e3d8d39c5cc0ec8a72119517e
2005-11-25Virtualize sinicNathan Binkert
separate the rx thread and tx thread and get rid of the dedicated flag. dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: python/m5/objects/Ethernet.py: dedicated flag goes away, we have new individual flags for rx thread and tx thread dev/sinic.cc: Virtualize sinic - The io registers are replicated many times in memory, allowing the NIC to differentiate among several virtual interfaces. - On the TX side, this allows multiple CPUs to initiate transmits at the same time without locking in the software. If a partial packet is transmitted, then the state machine blocks waiting for that virtual interface to complete its packet. Then the state machine will move on to the next virtual interface. The commands are kept in fifo order. - On the RX side, multiple partial transmits can be simultaneously done. Though a packet does not deallocate its fifo space until all preceeding packets in the fifo are deallocated. To enable multiple receives, it is necessary for each virtual nic to keep its own information about its progress through the state machine. dev/sinic.hh: Virtualize sinic Receive state must be virtualized since we allow the receipt of packets in parallel. dev/sinicreg.hh: Virtualize sinic separate rx thread and tx thread create a soft interrupt and add a command to trigger it. pad out the reserved bits in the RxDone and TxDone regs --HG-- extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
2005-11-25Add the capability to iterate through the packets in a pktfifo,Nathan Binkert
and to remove elements in the middle of the fifo. These elements do not free space, they are just marked removed. Space is only freed from the front of the fifo. dev/etherpkt.cc: serialize the current slack dev/etherpkt.hh: add "slack" to the ethernet packet. It is to be used by any fifo that the packet is currently in to account for extra space that the packet may be occupying due to the fifo organization. --HG-- extra : convert_revision : 8e7c541ba316a9a76495c54cc5f707f8fc65b6d5
2005-11-22add the cpu number of the request to various panic and traceNathan Binkert
output for sinic dev/sinic.cc: add the cpu number of the request to various panic and trace output --HG-- extra : convert_revision : e778a5c925e194652bec47af678488acf48c1ae0
2005-11-21add support for delaying pio writes until the cache access occursNathan Binkert
dev/ns_gige.cc: add support for delaying pio writes until the cache access occurs the only write we delay are for CR_TXE and CR_RXE dev/sinic.cc: dev/sinic.hh: the txPioRequest and rxPioRequest things were more or less bogus add support for delaying pio writes until the cache access occurs dev/sinicreg.hh: Add delay_read and delay_write to the register information struct for now, we won't delay any reads, and we'll delay the writes that initiate DMAs python/m5/objects/Ethernet.py: add a parameter to delay pio writes until the timing access actually occurs. --HG-- extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
2005-11-21have sinic use the new readBar/writeBar stuff that's in theNathan Binkert
pci device base class dev/sinic.cc: dev/sinic.hh: use the new readBar/writeBar stuff that's in the pci device base class --HG-- extra : convert_revision : 8a0b2bde3cc13597785d6ea75d6e6811680bb01b
2005-11-21Add a bunch of functions to manage the BAR addresses. ThisNathan Binkert
makes it easier to implement PCI device models. dev/pcidev.cc: default implementations for read/write and readBarX/writeBarX functions --HG-- extra : convert_revision : bbe2e2a2a506e2dd94d98f8e0feaefef96380be9
2005-11-20io_bus is split out into pio_bus and dma_bus so that any deviceNathan Binkert
can specify either independently. python/m5/objects/Device.py: io_bus is split out into pio_bus and dma_bus so that any device can specify either independently. dma_bus defaults to point to whatever pio_bus uses. --HG-- extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
2005-11-11Update random come to always have explict min/maxAli Saidi
--HG-- extra : convert_revision : a2d1f6f8aa1df24ea524792f687f4d3ee31101f0
2005-11-02Don't call Random.uniform() unnecessarilyAli Saidi
--HG-- extra : convert_revision : 82b092391f7c866f33ddb028070181038bdce0f8
2005-11-02Merge zizzer:/bk/m5Ali Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5 --HG-- extra : convert_revision : 3cc23080d19cc464a8ba7c1c93b6e5d45af7d463
2005-11-02Add ability to slightly perturb latency of ethernet/memoryAli Saidi
base/random.cc: Change normal random function to Xrand48 so we have one source of randomness for everything. base/random.hh: Add uniform distribution ability to random functions dev/etherlink.cc: dev/etherlink.hh: Add ability to slightly perturb latency of ethernet --HG-- extra : convert_revision : f7f856761fd525c233ae2a6d993b1fd702b488f7
2005-10-21Major changes to sinic device model. Rearrage read/write, betterNathan Binkert
interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-21missed another pio interface nameNathan Binkert
dev/sinic.cc: better name for both pio interfaces --HG-- extra : convert_revision : f7821c9c28b0095b366177b4c48a4ec14c3c89ee
2005-10-21better naming for pio interfacesNathan Binkert
dev/ns_gige.cc: why call it pio2 when there's only one? dev/sinic.cc: Give the interface a different name for stats/output purposes --HG-- extra : convert_revision : 895732f1a7e4c53e058a42b51320c2115dc05638
2005-10-21It's not necessary for a device to call recvDone, thatNathan Binkert
automatically happens in the interface after the packet is delivered to the device. --HG-- extra : convert_revision : 07890c4c5ce83fe709ce203f66c330d7cd631235
2005-10-18Shuffle around device names to make things easier to read.Nathan Binkert
Create EtherDevBase which both Sinic and NSGigE derive from bump fifos drop rx max copy size to 1514 bytes to be friendlier with linux default interrupt delay is 10us dev/ns_gige.cc: Shuffle around parameters to make it easier to find stuff dev/sinic.cc: Shuffle around parameters to make it easier to find stuff rename cycleTime -> clock dev/sinic.hh: rename cycleTime -> clock --HG-- extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7
2005-10-18use the dedicated flag, no more exposing the m5reg directlyNathan Binkert
dev/ns_gige.cc: stop exposing the m5reg to the configuration stuff and build it based on exposed flags. Expose dedicated now. dev/ns_gige.hh: goodbye m5reg hello dedicated dev/ns_gige_reg.h: Flags for the M5REG --HG-- extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3
2005-10-12better english in stat descriptions for NS GigENathan Binkert
dev/ns_gige.cc: better english in stat descriptions --HG-- extra : convert_revision : e75fc71e3285389cd38a9a00376a494778536b1d
2005-10-12Add support for 64-bit addresses to the NS GigE device model.Nathan Binkert
dev/ns_gige.cc: Add support for 64-bit addresses dev/ns_gige.hh: dev/ns_gige_reg.h: Need both cached 32-bit and 64-bit descriptors --HG-- extra : convert_revision : 514788d8d95554b3512f1b75db5314c823453a8c
2005-09-29fix for delayed state machine changesAli Saidi
--HG-- extra : convert_revision : db19e3687f48799725a9062e014588d318988cee
2005-09-24Fix IDE disk UDMA mode support mask to actually reflect support forSteve Reinhardt
modes 4 *and below*, not just mode 4. dev/ide_disk.cc: Fix UDMA mode support mask to actually reflect support for modes 4 *and below*, not just mode 4. --HG-- extra : convert_revision : 3506d503a5e8ce8a8686fb3a552383d365be0d41
2005-09-18Tweak the set of coalesced interruptsNathan Binkert
dev/ns_gige.cc: clean up usage of ISR_FOO macros dev/ns_gige_reg.h: Clean up #defines make ISR_RXIDLE and ISR_TXIDLE coalesced --HG-- extra : convert_revision : fd64fc6a441d096fc45737fdcb837de8868ca10a
2005-09-17Fix the EtherDump parametersNathan Binkert
dev/etherdump.cc: no default parameters anymore they should be in python python/m5/objects/Ethernet.py: move the maxlen parameter for EtherDump into python --HG-- extra : convert_revision : a796353a68907dfeb22059cd3ad536e6e8f60998
2005-09-12only set an approriately sized piece of data. so break where appropriateAli Saidi
Again... how did this work? --HG-- extra : convert_revision : 06dcab4ac9f5760c9847d0fa47fea67c4a46544a
2005-09-12fixes for gcc 4.0Ali Saidi
base/mysql.hh: include mysql_version to get rid of that annoying mysql error. make sure refcount is set in all constructors base/pollevent.hh: dev/ethertap.hh: dev/pciconfigall.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: sim/param.cc: fix for gcc 4 --HG-- extra : convert_revision : be626af2f40ca402818996ef27249ae256c63ef1
2005-08-23Lots of fixes to serialization and naming of various deviceNathan Binkert
objects. The improper serialization of arrays was particularly bad. dev/alpha_console.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: the pio interface is a different simobject and should have a different name. dev/ethertap.cc: fix serialization. dev/ide_ctrl.cc: - the pio interface is a different simobject and should have a different name. - properly initialize variables - When serializing an array, the size is the number of elements, not the number of bytes! dev/pcidev.cc: When serializing an array, the size is the number of elements, not the number of bytes! dev/tsunami_io.hh: Don't make objects SimObjects if they're not exposed to python. Don't add serialization functions to events, it's generally not what you want. allow the real time clock and interval timer to serialize themselves, must pass a base name since it is not a SimObject and the values will be going into the section of the parent. --HG-- extra : convert_revision : 3fc5de9b858ed770c8f385cf38b53242cf859c33
2005-08-23don't use sprintf. It's not guaranteed to not scribble over memory.Nathan Binkert
base/remote_gdb.cc: use snprintf, it's safer dev/ide_disk.cc: use strncpy instead of snprintf --HG-- extra : convert_revision : 90455e3f6bcb4c771724298a5a0b79a5b483a85c
2005-08-19A few minor fixes to get things to build on Cygwin.Steve Reinhardt
README: Clarify cygwin EIO error explanation. build/SConstruct: Cygwin header files cause uninitialized var warnings. dev/ide_ctrl.cc: Get rid of unnecessary byte-swap calls, some of which were too ambiguous for cygwin (or gcc 3.4.4). dev/pcidev.cc: Disambiguate arg for overloaded byte swap operation (and fix it to be the correct one). --HG-- extra : convert_revision : be37c6315aacbec6332b1d09e726b39b4aa18dce
2005-08-18Fix a couple of turbolaser problems that were introduced by theNathan Binkert
new freebsd code. dev/ns_gige.cc: g++ doesn't like it when you declare a variable inside a case label. Pull the declaration outside. --HG-- extra : convert_revision : d39e84fc58f2dd5b09c5948eedb4b1d7848e9817