gem5 - gem5

Age	Commit message (Collapse)	Author
2016-09-02	ext: eliminate warnings in SST connector	Curtis Dunham
	Now compiles completely clean.
2016-08-24	commit 15c633eea52f21dae8cb3a195823b3cdec7be491	Curtis Dunham
	Author: Curtis Dunham <Curtis.Dunham@arm.com> ext: update SST connector for SST 6.0
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
	In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
	The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
	In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
2016-02-04	ext: fix SST connector	Curtis Dunham
	Should work with SST 5.1 and trunk as of right now.
2016-01-29	ext: remove redundant parameter in example SST+gem5 test	Curtis Dunham
	The SST connector automatically adds --initialize-only to the gem5 "command line" (as it should); the config script doesn't need it.
2015-12-08	ext: fix SST connector	Curtis Dunham
	Writeback no longer a MemCmd.
2015-10-06	ext: fix SST connector	Curtis Dunham
	The renamings in changesets 8f5993cf (2015-03-23) "mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW" and fdd4a895 (2015-07-03) "mem: Split WriteInvalidateReq into write and invalidate" broke the SST connector. This commit repeats those renamings in ext/sst.
2015-04-08	config: Support full-system with SST's memory system	Curtis Dunham
	This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
2015-04-08	ext: Add SST connector	Curtis Dunham
	This patch adds a connector that allows gem5 to be used as a component in SST (Structural Simulation Toolkit, sst-simulator.org). At a high level, this allows memory traffic to pass between the two simulators. SST Links are roughly analogous to gem5 Ports, although Links do not have a notion of master and slave. This distinction is important to gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used, and similarly when connecting the memory side of SST cache to a gem5 port (for memory <-> I/O), an ExternalMaster must be used. These connectors handle the administrative aspects of gem5 (initialization, simulation, shutdown) as well as translating SST's MemEvents into gem5 Packets and vice-versa.