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dev/sinic.cc:
dev/sinic.hh:
Fix sinic parameters. (header_bus -> io_bus)
python/m5/objects/Ethernet.mpy:
Add simobj definitions for sinic.
--HG--
extra : convert_revision : 77d5b80bd1f1708329b263fb48965d7f555cc9d1
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cache from the cpu-side interface
--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
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can pass simulator specific options to the device driver.
dev/ns_gige.cc:
Add the m5 register and parameter to the ns83820 device model
so that we can pass simulator specific options to the device
driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
Add the m5 register to the ns83820 device model
--HG--
extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
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CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
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way ranges work, more fully support metric prefixes for all
integer types, and convert memory sized parameters to the
MemorySize type.
python/m5/config.py:
- no more _Param and _ParamProxy stuff. Use the names
ParamBase and ParamFactory to hopefully make it clearer
what we intend.
- Get rid of RangeSize and the old Range class and more fully flesh
out the Range class to deal with types of parameters and different
kinds of ranges.
- Call toInteger on the CheckedInt types so we can use metric prefixes
in strings for all integers.
- Get rid of the K, M, and G constants. Use the proper type or call
one of the functions in the convert package.
python/m5/convert.py:
Simple way to deal with both floating point and integer strings.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ethernet.mpy:
This is a MemorySize typed parameter
--HG--
extra : convert_revision : 92b4ea662d723abdd6c0a49065b79c25400fac9b
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python/m5/config.py:
- Enhanced Proxy class now supports subscripting, e.g.,
parent.cpu[0] or even parent.cpu[0].icache.
- Proxy also supports multiplication (e.g., parent.cycle * 3),
though this feature has not been tested.
- Subscript 0 works even on non-lists, so you can safely say
cpu[0] and get the first cpu even if there's only one.
- Changed name of proxy object from 'Super' to 'parent', and
changed "wild card" notation from plain 'Super' to 'parent.any'.
python/m5/objects/AlphaConsole.mpy:
python/m5/objects/BaseCPU.mpy:
python/m5/objects/BaseSystem.mpy:
python/m5/objects/Device.mpy:
python/m5/objects/Ethernet.mpy:
python/m5/objects/Ide.mpy:
python/m5/objects/IntrControl.mpy:
python/m5/objects/Pci.mpy:
python/m5/objects/PhysicalMemory.mpy:
python/m5/objects/Platform.mpy:
python/m5/objects/SimConsole.mpy:
python/m5/objects/SimpleDisk.mpy:
python/m5/objects/Tsunami.mpy:
python/m5/objects/Uart.mpy:
Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any').
--HG--
extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d
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create an m5 package in python/m5
move the objects package into the m5 package
move the m5config into the m5 package as config
leave both importers outside of the package.
SConscript:
sim/main.cc:
move sim/pyconfig/* -> python
python/SConscript:
m5config.py -> m5/config.py (now automatically embedded)
objects -> python/m5/objects
embed all python files in python/m5
python/m5/config.py:
importer renamed mpy_importer
move code to m5/__init__.py
test/genini.py:
deal with new python organization
keep track of paths we want to add and add them after parameters
are parsed.
--HG--
rename : sim/pyconfig/SConscript => python/SConscript
rename : sim/pyconfig/m5config.py => python/m5/config.py
rename : objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.mpy
rename : objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.mpy
rename : objects/BadDevice.mpy => python/m5/objects/BadDevice.mpy
rename : objects/BaseCPU.mpy => python/m5/objects/BaseCPU.mpy
rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy
rename : objects/BaseSystem.mpy => python/m5/objects/BaseSystem.mpy
rename : objects/Bus.mpy => python/m5/objects/Bus.mpy
rename : objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.mpy
rename : objects/Device.mpy => python/m5/objects/Device.mpy
rename : objects/DiskImage.mpy => python/m5/objects/DiskImage.mpy
rename : objects/Ethernet.mpy => python/m5/objects/Ethernet.mpy
rename : objects/Ide.mpy => python/m5/objects/Ide.mpy
rename : objects/IntrControl.mpy => python/m5/objects/IntrControl.mpy
rename : objects/MemTest.mpy => python/m5/objects/MemTest.mpy
rename : objects/Pci.mpy => python/m5/objects/Pci.mpy
rename : objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.mpy
rename : objects/Platform.mpy => python/m5/objects/Platform.mpy
rename : objects/Process.mpy => python/m5/objects/Process.mpy
rename : objects/Repl.mpy => python/m5/objects/Repl.mpy
rename : objects/Root.mpy => python/m5/objects/Root.mpy
rename : objects/SimConsole.mpy => python/m5/objects/SimConsole.mpy
rename : objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.mpy
rename : objects/Tsunami.mpy => python/m5/objects/Tsunami.mpy
rename : objects/Uart.mpy => python/m5/objects/Uart.mpy
extra : convert_revision : aebf6ccda33028b1125974ca8b6aeab6f7570f30
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