| Age | Commit message (Expand) | Author |
|---|
| 2019-10-19 | arch: Remove the "interrupts.hh" switching header file. | Gabe Black |
| 2019-04-30 | arch: Remove the mt.hh switching header. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2018-01-23 | arch: Remove the "arch/tlb.hh" switching header. | Gabe Black |
| 2017-11-10 | scons: Move Transform and termcap functionality into their own files. | Gabe Black |
| 2017-10-17 | scons: Stop generating inc.d in the isa parser. | Gabe Black |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-05-10 | scons: Use the generalized switching headers on the GPU ISA. | Gabe Black |
| 2017-05-10 | scons: arch: Generalize the switching header code. | Gabe Black |
| 2016-10-26 | gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF | Tony Gutierrez |
| 2016-01-19 | gpu-compute: AMD's baseline GPU model | Tony Gutierrez |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2014-11-23 | kvm, x86: Adding support for SE mode execution | Alexandru Dutu |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-05-09 | arch: teach ISA parser how to split code across files | Curtis Dunham |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-04-23 | ISA: Put parser generated files in a "generated" directory. | Gabe Black |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-02-07 | Faults: Turn off arch/faults.hh | Gabe Black |
| 2011-09-24 | SCons: Add a comment I forgot to add in earlier. | Gabe Black |
| 2011-09-24 | SCons: Make the ISA parser a source for its output files like the comments say. | Gabe Black |
| 2011-06-02 | scons: rename TraceFlags to DebugFlags | Nathan Binkert |
| 2011-03-01 | Spelling: Fix the a spelling error by changing mmaped to mmapped. | Gabe Black |
| 2011-01-07 | scons: show sources and targets when building, and colorize output. | Steve Reinhardt |
| 2010-12-20 | Style: Replace some tabs with spaces. | Gabe Black |
| 2010-11-15 | SCons: Cleanup SCons output during compile | Ali Saidi |
| 2010-08-22 | X86: Get rid of unused file arguments.hh. | Gabe Black |
| 2010-03-10 | scons: import ply to work around scons sys.path weirdness | Nathan Binkert |
| 2010-02-26 | cpu_models: get rid of cpu_models.py and move the stuff into SCons | Nathan Binkert |
| 2010-02-26 | isa_parser: Make SCons import the isa_parser | Nathan Binkert |
| 2009-07-08 | Registers: Add a registers.hh file as an ISA switched header. | Gabe Black |
| 2009-07-08 | Registers: Add an ISA object which replaces the MiscRegFile. | Gabe Black |
| 2009-05-12 | inorder-alpha-port: initial inorder support of ALPHA | Korey Sewell |
| 2009-02-27 | Processes: Make getting and setting system call arguments part of a process o... | Gabe Black |
| 2009-02-25 | ISA: Set up common trace flags for tracing registers. | Gabe Black |
| 2008-10-12 | CPU: Create a microcode ROM object in the CPU which is defined by the ISA. | Gabe Black |
| 2007-11-08 | ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs. | Gabe Black |
| 2007-07-28 | style: Check/Fix whitespace on SCons files | Nathan Binkert |
| 2007-03-15 | Merge zizzer.eecs.umich.edu:/bk/newmem | Gabe Black |
| 2007-03-15 | Make the predecoder an object with it's own switched header file. Start addin... | Gabe Black |
| 2007-03-10 | Rework the way SCons recurses into subdirectories, making it | Nathan Binkert |
| 2006-11-29 | Add support for mmapped iprs to atomic cpu | Ali Saidi |
| 2006-11-07 | Put kernel_stats back into arch. | Gabe Black |
| 2006-11-07 | Made kern a switching header file directory. | Gabe Black |
| 2006-11-06 | Remote GDB support has been changed to use inheritance. Alpha should work, bu... | Gabe Black |
| 2006-11-03 | Add a new file which describes an ISA's interrupt handling mechanism. It reco... | Gabe Black |
| 2006-10-08 | Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) | Steve Reinhardt |
