gem5 - gem5

Age	Commit message (Expand)	Author
2009-07-08	Registers: Eliminate the ISA defined floating point register file.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
2008-10-12	Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...	Gabe Black
2007-11-08	CPU: Add function to explictly compare thread contexts after copying.	Ali Saidi
2007-10-31	Traceflags: Add SCons function to created a traceflag instead of having one f...	Ali Saidi
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-01	Arguments: Get rid of duplicate code for the Arguments class in each architec...	Ali Saidi
2007-05-27	Move SimObject python files alongside the C++ and fix	Nathan Binkert
2007-03-10	Rework the way SCons recurses into subdirectories, making it	Nathan Binkert
2006-12-20	Initial work to make remote gdb available in SE mode. This is completely unte...	Gabe Black
2006-11-10	Moved the Alpha float regfile into it's own regfile and got rid of constants....	Gabe Black
2006-11-10	Split out alpha integer register file into it's own files.	Gabe Black
2006-11-09	Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha spec...	Gabe Black
2006-11-07	Put kernel_stats back into arch.	Gabe Black
2006-11-06	Remote GDB support has been changed to use inheritance. Alpha should work, bu...	Gabe Black
2006-10-31	Make the IPRs use regular miscreg indexes, and make a table or two to find th...	Gabe Black
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-22	New directory structure:	Steve Reinhardt