gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-31	alpha: Stop using architecture specific register types.	Gabe Black
2019-01-22	arch: cpu: Stop passing around misc registers by reference.	Gabe Black
2017-12-04	misc: Rename misc.(hh\|cc) to logging.(hh\|cc)	Gabe Black
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2010-09-14	CPU: Trim unnecessary includes from some common files.	Gabe Black
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2009-10-17	ISA: Fix compilation.	Gabe Black
2009-07-08	Alpha: Pull the MiscRegFile fully into the ISA object.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black