gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2014-01-24	arch: Make all register index flattening const	Andreas Hansson
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-02-19	scons: Add warning for overloaded virtual functions	Andreas Hansson
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-26	mips: cleanup ISA-specific code	Korey Sewell
2010-10-10	SPARC: Make SPARC's ISA's clear function initialize everything it should.	Gabe Black
2010-10-10	Alpha: Force all the IPRs to an initial, determinstic value when cleared.	Gabe Black
2009-10-17	ISA: Fix compilation.	Gabe Black
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-07-08	Alpha: Pull the MiscRegFile fully into the ISA object.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black