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path: root/src/arch/alpha/isa
AgeCommit message (Expand)Author
2011-07-07alpha:hwrei:rollback for o3Korey Sewell
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-06-19alpha: fix warn_once for prefetchesKorey Sewell
2011-06-19alpha: make hwrei a control instKorey Sewell
2011-04-15includes: sort all includesNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-08Alpha: Take advantage of new PCState syntax.Gabe Black
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-22ISA: Simplify various implementations of completeAcc.Gabe Black
2010-03-23cpu: fix exec tracing memory corruption bugSteve Reinhardt
2009-12-20Alpha: Implement MVI and remaining BWX instructions.Soumyaroop Roy
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-07-08Alpha: Pull the MiscRegFile fully into the ISA object.Gabe Black
2009-07-08Alpha: Move reg_redir into its own files, and move some constants into regfil...Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
2009-05-12inorder-mem: skeleton support for prefetch/writehintsKorey Sewell
2009-05-12inorder/alpha-isa: create eaComp object visible to StaticInst through ISAKorey Sewell
2009-05-12inorder-alpha-port: initial inorder support of ALPHAKorey Sewell
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-02-26CPA: Add new object for gathering critical path annotations.Ali Saidi
2009-01-24pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.Nathan Binkert
2008-12-17Make Alpha pseudo-insts available from SE mode.Steve Reinhardt
2008-11-14Fix a bunch of bugs I introduced when I changed the flags stuff for packets.Nathan Binkert
2008-11-10pseudo inst: Add rpns (read processor nanoseconds) instruction.Nathan Binkert
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-09-27alpha: Clean up namespace usage.Nathan Binkert
2008-09-27alpha: Get rid fo the namespace called EV5.Nathan Binkert
2008-07-11m5ops: clean up the m5ops stuff.Nathan Binkert
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
2007-04-21create base/fenv.c to standerdize fenv across platforms. It's a c file and no...Ali Saidi
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Make hardware loads/stores serializing; they need to avoid certain out-of-ord...Kevin Lim
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2007-02-21add pseduo instruction support for sparcAli Saidi
2007-02-12Merge zizzer:/bk/newmemAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-12Move store conditional result checking from SimpleAtomicCpu writeSteve Reinhardt
2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
2006-11-24Add no-op versions of ivlb and ivle back in for backwards compatibility.Steve Reinhardt
2006-11-09Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha spec...Gabe Black
2006-11-06Got rid of obsolete ivlb and ivle psuedo instructions.Gabe Black