gem5 - gem5

Age	Commit message (Expand)	Author
2011-07-07	alpha:hwrei:rollback for o3	Korey Sewell
2011-07-05	ISA parser: Define operand types with a ctype directly.	Gabe Black
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black
2011-06-19	alpha: fix warn_once for prefetches	Korey Sewell
2011-06-19	alpha: make hwrei a control inst	Korey Sewell
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-12-20	Style: Replace some tabs with spaces.	Gabe Black
2010-12-08	Alpha: Take advantage of new PCState syntax.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-22	ISA: Simplify various implementations of completeAcc.	Gabe Black
2010-03-23	cpu: fix exec tracing memory corruption bug	Steve Reinhardt
2009-12-20	Alpha: Implement MVI and remaining BWX instructions.	Soumyaroop Roy
2009-11-10	Mem: Eliminate the NO_FAULT request flag.	Gabe Black
2009-07-08	Alpha: Pull the MiscRegFile fully into the ISA object.	Gabe Black
2009-07-08	Alpha: Move reg_redir into its own files, and move some constants into regfil...	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell
2009-05-12	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA	Korey Sewell
2009-05-12	inorder-alpha-port: initial inorder support of ALPHA	Korey Sewell
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-02-26	CPA: Add new object for gathering critical path annotations.	Ali Saidi
2009-01-24	pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.	Nathan Binkert
2008-12-17	Make Alpha pseudo-insts available from SE mode.	Steve Reinhardt
2008-11-14	Fix a bunch of bugs I introduced when I changed the flags stuff for packets.	Nathan Binkert
2008-11-10	pseudo inst: Add rpns (read processor nanoseconds) instruction.	Nathan Binkert
2008-11-10	mem: update stuff for changes to Packet and Request	Nathan Binkert
2008-10-20	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...	Ali Saidi
2008-10-11	CPU: Eliminate the simPalCheck funciton.	Gabe Black
2008-10-11	CPU: Eliminate the hwrei function.	Gabe Black
2008-09-27	alpha: Clean up namespace usage.	Nathan Binkert
2008-09-27	alpha: Get rid fo the namespace called EV5.	Nathan Binkert
2008-07-11	m5ops: clean up the m5ops stuff.	Nathan Binkert
2007-07-31	Add a flag to indicate an instruction triggers a syscall in SE mode.	Gabe Black
2007-04-21	create base/fenv.c to standerdize fenv across platforms. It's a c file and no...	Ali Saidi
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	Make hardware loads/stores serializing; they need to avoid certain out-of-ord...	Kevin Lim
2007-03-07	MiscReg->MiscRegNoEffect, MiscRegWithEffect->MiscReg	Ali Saidi
2007-02-21	add pseduo instruction support for sparc	Ali Saidi
2007-02-12	Merge zizzer:/bk/newmem	Ali Saidi
2007-02-12	rename store conditional stuff as extra data so it can be used for conditiona...	Ali Saidi
2007-02-12	Move store conditional result checking from SimpleAtomicCpu write	Steve Reinhardt
2006-12-17	Convert Alpha (and finish converting MIPS) to new	Steve Reinhardt
2006-11-24	Add no-op versions of ivlb and ivle back in for backwards compatibility.	Steve Reinhardt
2006-11-09	Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha spec...	Gabe Black
2006-11-06	Got rid of obsolete ivlb and ivle psuedo instructions.	Gabe Black