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path: root/src/arch/alpha/isa
AgeCommit message (Expand)Author
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-02-26CPA: Add new object for gathering critical path annotations.Ali Saidi
2009-01-24pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.Nathan Binkert
2008-12-17Make Alpha pseudo-insts available from SE mode.Steve Reinhardt
2008-11-14Fix a bunch of bugs I introduced when I changed the flags stuff for packets.Nathan Binkert
2008-11-10pseudo inst: Add rpns (read processor nanoseconds) instruction.Nathan Binkert
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-09-27alpha: Clean up namespace usage.Nathan Binkert
2008-09-27alpha: Get rid fo the namespace called EV5.Nathan Binkert
2008-07-11m5ops: clean up the m5ops stuff.Nathan Binkert
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
2007-04-21create base/fenv.c to standerdize fenv across platforms. It's a c file and no...Ali Saidi
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Make hardware loads/stores serializing; they need to avoid certain out-of-ord...Kevin Lim
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2007-02-21add pseduo instruction support for sparcAli Saidi
2007-02-12Merge zizzer:/bk/newmemAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-12Move store conditional result checking from SimpleAtomicCpu writeSteve Reinhardt
2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
2006-11-24Add no-op versions of ivlb and ivle back in for backwards compatibility.Steve Reinhardt
2006-11-09Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha spec...Gabe Black
2006-11-06Got rid of obsolete ivlb and ivle psuedo instructions.Gabe Black
2006-11-01Fix a range check on the ipr_index.Gabe Black
2006-11-01Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...Gabe Black
2006-10-31Arg!Gabe Black
2006-10-31More typos! I need to get nfs to work.Gabe Black
2006-10-31Fix another typoGabe Black
2006-10-31Check for out of range IPR values as well.Gabe Black
2006-10-31Make two simple utility functions to determine if a MiscReg index correspondi...Gabe Black
2006-10-31Forgot to change the index.Gabe Black
2006-10-31Make the IPRs use regular miscreg indexes, and make a table or two to find th...Gabe Black
2006-10-31Move IntrFlag into the MiscRegFile and get rid of specialized accessor functi...Gabe Black
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-06there are two main thrusts of this changeset.Lisa Hsu
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-09-11add annotation code to m5Ali Saidi
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-06-16Add in exec_context.hh, which is a file for documentation purposes only. It ...Kevin Lim
2006-06-13Make syscalls serialize after instructions so they work properly on the new C...Kevin Lim
2006-06-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-06-12Fixes for checker. The RC/RS instructions check the interrupt flag, which is...Kevin Lim
2006-06-09Merge vm1.(none):/home/stever/bk/newmemSteve Reinhardt
2006-06-09Move main control from C++ into Python.Steve Reinhardt
2006-06-06Change ExecContext to ThreadContext. This is being renamed to differentiate ...Kevin Lim
2006-06-02Merge ktlim@zizzer:/bk/newmemKevin Lim
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