gem5 - gem5

Age	Commit message (Expand)	Author
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell
2009-05-12	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA	Korey Sewell
2009-05-12	inorder-alpha-port: initial inorder support of ALPHA	Korey Sewell
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-02-26	CPA: Add new object for gathering critical path annotations.	Ali Saidi
2009-01-24	pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.	Nathan Binkert
2008-12-17	Make Alpha pseudo-insts available from SE mode.	Steve Reinhardt
2008-11-14	Fix a bunch of bugs I introduced when I changed the flags stuff for packets.	Nathan Binkert
2008-11-10	pseudo inst: Add rpns (read processor nanoseconds) instruction.	Nathan Binkert
2008-11-10	mem: update stuff for changes to Packet and Request	Nathan Binkert
2008-10-20	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...	Ali Saidi
2008-10-11	CPU: Eliminate the simPalCheck funciton.	Gabe Black
2008-10-11	CPU: Eliminate the hwrei function.	Gabe Black
2008-09-27	alpha: Clean up namespace usage.	Nathan Binkert
2008-09-27	alpha: Get rid fo the namespace called EV5.	Nathan Binkert
2008-07-11	m5ops: clean up the m5ops stuff.	Nathan Binkert
2007-07-31	Add a flag to indicate an instruction triggers a syscall in SE mode.	Gabe Black
2007-04-21	create base/fenv.c to standerdize fenv across platforms. It's a c file and no...	Ali Saidi
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	Make hardware loads/stores serializing; they need to avoid certain out-of-ord...	Kevin Lim
2007-03-07	MiscReg->MiscRegNoEffect, MiscRegWithEffect->MiscReg	Ali Saidi
2007-02-21	add pseduo instruction support for sparc	Ali Saidi
2007-02-12	Merge zizzer:/bk/newmem	Ali Saidi
2007-02-12	rename store conditional stuff as extra data so it can be used for conditiona...	Ali Saidi
2007-02-12	Move store conditional result checking from SimpleAtomicCpu write	Steve Reinhardt
2006-12-17	Convert Alpha (and finish converting MIPS) to new	Steve Reinhardt
2006-11-24	Add no-op versions of ivlb and ivle back in for backwards compatibility.	Steve Reinhardt
2006-11-09	Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha spec...	Gabe Black
2006-11-06	Got rid of obsolete ivlb and ivle psuedo instructions.	Gabe Black
2006-11-01	Fix a range check on the ipr_index.	Gabe Black
2006-11-01	Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...	Gabe Black
2006-10-31	Arg!	Gabe Black
2006-10-31	More typos! I need to get nfs to work.	Gabe Black
2006-10-31	Fix another typo	Gabe Black
2006-10-31	Check for out of range IPR values as well.	Gabe Black
2006-10-31	Make two simple utility functions to determine if a MiscReg index correspondi...	Gabe Black
2006-10-31	Forgot to change the index.	Gabe Black
2006-10-31	Make the IPRs use regular miscreg indexes, and make a table or two to find th...	Gabe Black
2006-10-31	Move IntrFlag into the MiscRegFile and get rid of specialized accessor functi...	Gabe Black
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-19	refactor code for the packet, get rid of packet_impl.hh	Nathan Binkert
2006-10-06	there are two main thrusts of this changeset.	Lisa Hsu
2006-09-30	Merge ktlim@zamp:./local/clean/o3-merge/m5	Kevin Lim
2006-09-11	add annotation code to m5	Ali Saidi
2006-07-23	This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...	Korey Sewell
2006-06-16	Add in exec_context.hh, which is a file for documentation purposes only. It ...	Kevin Lim
2006-06-13	Make syscalls serialize after instructions so they work properly on the new C...	Kevin Lim
2006-06-12	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-06-12	Fixes for checker. The RC/RS instructions check the interrupt flag, which is...	Kevin Lim