index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
alpha
/
locked_mem.hh
Age
Commit message (
Expand
)
Author
2014-01-24
cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...
Ali Saidi
2013-01-07
o3: Fix issue with LLSC ordering and speculation
Ali Saidi
2010-12-07
O3: Make all instructions that write a misc. register not perform the write u...
Giacomo Gabrielli
2009-07-08
Alpha: Pull the MiscRegFile fully into the ISA object.
Gabe Black
2008-11-02
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
Lisa Hsu
2008-11-02
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
Lisa Hsu
2008-09-27
style: Make a style pass over the whole arch/alpha directory.
Nathan Binkert
2007-03-07
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
Ali Saidi
2007-02-12
Merge zizzer:/bk/newmem
Ali Saidi
2007-02-12
rename store conditional stuff as extra data so it can be used for conditiona...
Ali Saidi
2007-02-12
Move store conditional result checking from SimpleAtomicCpu write
Steve Reinhardt
2006-11-09
Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha spec...
Gabe Black
2006-10-08
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
Steve Reinhardt
