gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-31	arch: cpu: Rename FloatRegBits to FloatReg.	Gabe Black
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-01-29	Implement Ali's review feedback.	Gabe Black
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-11-01	SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.	Gabe Black
2011-05-13	Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.	Chander Sudanthi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-15	GetArgument: Rework getArgument so that X86_FS compiles again.	Gabe Black
2010-10-01	Debug: Implement getArgument() and function skipping for ARM.	Ali Saidi
2009-07-08	Alpha: Pull the MiscRegFile fully into the ISA object.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-02-27	Processes: Make getting and setting system call arguments part of a process o...	Gabe Black
2008-09-27	style: Make a style pass over the whole arch/alpha directory.	Nathan Binkert
2008-07-01	Remove delVirtPort() and make getVirtPort() only return cached version.	Ali Saidi
2008-07-01	Change everything to use the cached virtPort rather than created their own ea...	Ali Saidi
2007-08-01	Arguments: Get rid of duplicate code for the Arguments class in each architec...	Ali Saidi