summaryrefslogtreecommitdiff
path: root/src/arch/alpha
AgeCommit message (Collapse)Author
2009-10-30Syscalls: Make system calls access arguments like a stack, not an array.Gabe Black
When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job.
2009-10-24syscall: Addition of an ioctl command code for Power.Timothy M. Jones
2009-10-17ISA: Fix compilation.Gabe Black
2009-09-15Syscalls: Implement sysinfo() syscall.Vince Weaver
2009-07-09Alpha: Missed a file in an earlier changeset.Gabe Black
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Alpha: Pull the MiscRegFile fully into the ISA object.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08Alpha: Move reg_redir into its own files, and move some constants into ↵Gabe Black
regfile.hh.
2009-07-08Registers: Eliminate the ISA defined RegFile class.Gabe Black
2009-07-08Alpha: Get rid of function prototypes with no implementations.Gabe Black
2009-07-08Registers: Move the PCs out of the ISAs and into the CPUs.Gabe Black
2009-07-08Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.Gabe Black
2009-07-08Registers: Eliminate the ISA defined integer register file.Gabe Black
2009-07-08Registers: Eliminate the ISA defined floating point register file.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-05-12alpha-isa: add mt.hh so it can compile with inorderKorey Sewell
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12inorder-float: Fix storage of FP resultsKorey Sewell
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store
2009-05-12inorder-mem: skeleton support for prefetch/writehintsKorey Sewell
2009-05-12inorder-unified-tlb: use unified TLB instead of old TLB modelKorey Sewell
2009-05-12inorder/alpha-isa: create eaComp object visible to StaticInst through ISAKorey Sewell
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-05-12inorder-bpred: edits to handle non-delay-slot ISAsKorey Sewell
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12inorder-alpha-port: initial inorder support of ALPHAKorey Sewell
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)
2009-04-21syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.Steve Reinhardt
2009-04-21Commit m5threads package.Daniel Sanchez
This patch adds limited multithreading support in syscall-emulation mode, by using the clone system call. The clone system call works for Alpha, SPARC and x86, and multithreaded applications run correctly in Alpha and SPARC.
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-08alpha: get rid of all turbolaser remnantsNathan Binkert
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-03-05Get rid of 'using namespace' declarations in headers.Steve Reinhardt
2009-02-28Fix Num_Syscall_Descs check bug in non-x86 ISAs.Steve Reinhardt
(See cset d35d2b28df38 for x86 fix.)
2009-02-27Processes: Make getting and setting system call arguments part of a process ↵Gabe Black
object.
2009-02-26CPA: Add code to automatically record function symbols as CPU executes.Ali Saidi
2009-02-26CPA: Add new object for gathering critical path annotations.Ali Saidi
2009-02-25ISA: Get rid of the get*RegName functions.Gabe Black
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert ↵Gabe Black
the timing simple CPU to use it.
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-23debug: Move debug_break into src/baseNathan Binkert
2009-02-16sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has ↵Lisa Hsu
been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
2009-02-09scons: Require SCons version 0.98.1Nathan Binkert
This allows me to clean things up so we are up to date with respect to deprecated features. There are many features scheduled for permanent failure in scons 2.0 and 0.98.1 provides the most compatability for that. It also paves the way for some nice new features that I will add soon
2009-01-25CPU: Add a setCPU function to the interrupt objects.Gabe Black
2009-01-24pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.Nathan Binkert
It's instantaneous and so it's somewhat bogus, but it's a first step.
2008-12-17Make Alpha pseudo-insts available from SE mode.Steve Reinhardt