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2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one ↵Ali Saidi
file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-31Linux Support: Finally update vptr for new memory system.Ali Saidi
--HG-- extra : convert_revision : 8b4927431189abc12201d13428a31b746cdb7dee
2007-10-25TLB: Fix serialization issues with the tlb entries and make the page table ↵Gabe Black
store the process, not the system. --HG-- extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
2007-10-25SE: Fix page table and system serialization, don't reinit process if this is ↵Ali Saidi
a checkpoint restore. --HG-- extra : convert_revision : 03dcf3c088e57b7abab60efe700d947117888306
2007-10-16Make the process objects use the Params structs in their constructors, and ↵Gabe Black
use a limit to check if access are on the stack. --HG-- extra : convert_revision : af40a7acf424c4c4f62d0d76db1001a714ae0474
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
--HG-- extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
2007-09-19X86: Put in the foundation for x87 stack based fp registers.Gabe Black
--HG-- extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
2007-09-13Syscall Emulation: Add stat64 syscall.Ali Saidi
Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de] --HG-- extra : convert_revision : 07638c05bb3f79aacce49457bbb8c17d0a3a7238
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-27Alpha: Fixes to get alpha to compile again.Gabe Black
--HG-- extra : convert_revision : 9541cf6dae1fb1a1c6025898692b2e04fcf55c6d
2007-08-26Address translation: Make the page table more flexible.Gabe Black
The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. --HG-- extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-08alpha: Quick fix for things related to TLB MRU cache.Vincentius Robby
simple-timing test for ALPHA_FS breaks. --HG-- extra : convert_revision : 5a1b05cddd480849913da81a3b3931fec16485a8
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
Improve MRU checking for StaticInst, Bus, TLB --HG-- extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
2007-08-07Alpha: Fix an off by one error with the tlb caching mechanism.Gabe Black
--HG-- extra : convert_revision : e17f7a0d58a2e59b2e270f0827db33d0a29365e0
2007-08-04alpha: Implement a cache for recently used page table entriesVincentius Robby
--HG-- extra : convert_revision : 1bb80d71fa91e500a68390e5dc17464ce7136fba
2007-08-02Linux Support: make sure that when we get the stack page for thread info ↵Ali Saidi
we're doing a 64bit not --HG-- extra : convert_revision : c581921dd601fc72fd2d45b961c7440755b0331c
2007-08-01Merge Gabe and my changes to arch/mips/utility.hhAli Saidi
--HG-- extra : convert_revision : d5a9d74ee6edf71524ba5c03fb7f054cf9722213
2007-08-01Arguments: Get rid of duplicate code for the Arguments class in each ↵Ali Saidi
architecture. Move the argument files to src/sim and add a utility.cc file with a function getArguments() that returns the given argument in the architecture specific fashion. getArguments() was getArg() is the architecture specific Argument class and has had all magic numbers replaced with meaningful constants. Also add a function to the Argument class for testing if an argument is NULL. --HG-- rename : src/arch/alpha/arguments.cc => src/sim/arguments.cc rename : src/arch/alpha/arguments.hh => src/sim/arguments.hh extra : convert_revision : 8b93667bafaa03b52aadb64d669adfe835266b8e
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
--HG-- extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
2007-07-26X86: Fix argument register indexing.Gabe Black
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-22Merge Gabe's changes with mine.Steve Reinhardt
--HG-- extra : convert_revision : f50ed42e7acb3f11e610fd6976eaa8df0c6ba2ab
2007-07-18Make name, isMachineCheckFault, and isAlignmentFault const.Gabe Black
--HG-- extra : convert_revision : a27e0cbdfcb2a5fdc5979686f887cec7d106542b
2007-07-14Disable PrintThreadInfo since it causes a panic when using VPtr.Steve Reinhardt
See Flyspray #281. --HG-- extra : convert_revision : 199ef802bcabed09f6ea6922c3a3954fea161190
2007-06-19Make branches work by repopulating the predecoder every time through. This ↵Gabe Black
is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. --HG-- extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
2007-06-14Modified instruction decode method.Vincentius Robby
Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. --HG-- extra : convert_revision : a9a6d3a16fff59bc95d0606ea344bd57e71b8d0a
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the ↵Gabe Black
"moreBytes" which just takes a MachInst. src/arch/x86/predecoder.cc: Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes. --HG-- extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
2007-05-31Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/cpu/simple/base.cc: Hand merge --HG-- extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-18Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
2007-05-01fix flushAddr so it doesn't modify an iterator that has been deletedAli Saidi
--HG-- extra : convert_revision : 8b7e4948974517b13616ab782aa7e84471b24f10
2007-04-21fixes for solaris compileAli Saidi
--HG-- extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
2007-04-21create base/fenv.c to standerdize fenv across platforms. It's a c file and ↵Ali Saidi
not a cpp file because c99 (which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment. src/arch/alpha/isa/fp.isa: src/arch/sparc/isa/formats/basic.isa: use m5_fesetround()/m5_fegetround() istead of fenv interface directly src/arch/sparc/isa/includes.isa: use base/fenv instead of fenv directly src/base/SConscript: add fenv to sconscript src/base/fenv.hh: src/base/random.cc: m5 implementation to standerdize fenv across platforms. --HG-- extra : convert_revision : 38d2629affd964dcd1a5ab0db4ac3cb21438e72c
2007-04-11Make the itlb set the PHYSICAL flag on a request when it translates it. This ↵Gabe Black
gets it out of the cpu. --HG-- extra : convert_revision : 20611263b799b5e835116adbf39d2ecc78701eef
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23Make hardware loads/stores serializing; they need to avoid certain ↵Kevin Lim
out-of-order interactions in the 21264. --HG-- extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
2007-03-18Compile fixes for SPARC_FS.Gabe Black
src/arch/alpha/predecoder.hh: src/arch/sparc/predecoder.hh: Put in a missing include src/cpu/exetrace.cc: Convert the legion lockstep stuff from makeExtMI to the predecoder object. --HG-- extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge --HG-- extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
2007-03-15Make the predecoder an object with it's own switched header file. Start ↵Gabe Black
adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. --HG-- extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-13Replaced makeExtMI with predecode.Gabe Black
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-09implement ipi stufff for SPARCAli Saidi
src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not) --HG-- extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
2007-03-07Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same ↵Gabe Black
across all architectures. --HG-- extra : convert_revision : 18d441eb7ac44df4df41771bfe3dec69f7fa70ec
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
--HG-- extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
2007-03-04Don't use the exact same name as a system header #defineNathan Binkert
--HG-- extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
2007-03-03Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-02-28The "hostname" variable isn't used in the process classes. It should be ↵Gabe Black
removed from the other ones as well. --HG-- extra : convert_revision : 0c07534de42d6c32ac26d9e43709111e3ab30d57
2007-02-21Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 06:35:22 +0000