index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
alpha
Age
Commit message (
Expand
)
Author
2009-07-08
Registers: Eliminate the ISA defined floating point register file.
Gabe Black
2009-07-08
Registers: Get rid of the float register width parameter.
Gabe Black
2009-07-08
Registers: Add an ISA object which replaces the MiscRegFile.
Gabe Black
2009-06-04
types: clean up types, especially signed vs unsigned
Nathan Binkert
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2009-05-17
includes: sort includes again
Nathan Binkert
2009-05-17
types: Move stuff for global types into src/base/types.hh
Nathan Binkert
2009-05-12
alpha-isa: add mt.hh so it can compile with inorder
Korey Sewell
2009-05-12
inorder-tlb-cunit: merge the TLB as implicit to any memory access
Korey Sewell
2009-05-12
inorder-float: Fix storage of FP results
Korey Sewell
2009-05-12
inorder-mem: skeleton support for prefetch/writehints
Korey Sewell
2009-05-12
inorder-unified-tlb: use unified TLB instead of old TLB model
Korey Sewell
2009-05-12
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Korey Sewell
2009-05-12
inorder-bpred: edits to handle non-delay-slot ISAs
Korey Sewell
2009-05-12
inorder-alpha-port: initial inorder support of ALPHA
Korey Sewell
2009-04-21
syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
Steve Reinhardt
2009-04-21
Commit m5threads package.
Daniel Sanchez
2009-04-19
Memory: Rename LOCKED for load locked store conditional to LLSC.
Gabe Black
2009-04-08
alpha: get rid of all turbolaser remnants
Nathan Binkert
2009-04-08
tlb: More fixing of unified TLB
Nathan Binkert
2009-04-08
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Gabe Black
2009-03-05
stats: Fix all stats usages to deal with template fixes
Nathan Binkert
2009-03-05
Get rid of 'using namespace' declarations in headers.
Steve Reinhardt
2009-02-28
Fix Num_Syscall_Descs check bug in non-x86 ISAs.
Steve Reinhardt
2009-02-27
Processes: Make getting and setting system call arguments part of a process o...
Gabe Black
2009-02-26
CPA: Add code to automatically record function symbols as CPU executes.
Ali Saidi
2009-02-26
CPA: Add new object for gathering critical path annotations.
Ali Saidi
2009-02-25
ISA: Get rid of the get*RegName functions.
Gabe Black
2009-02-25
CPU: Implement translateTiming which defers to translateAtomic, and convert t...
Gabe Black
2009-02-25
ISA: Replace the translate functions in the TLBs with translateAtomic.
Gabe Black
2009-02-23
debug: Move debug_break into src/base
Nathan Binkert
2009-02-16
sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has bee...
Lisa Hsu
2009-02-09
scons: Require SCons version 0.98.1
Nathan Binkert
2009-01-25
CPU: Add a setCPU function to the interrupt objects.
Gabe Black
2009-01-24
pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.
Nathan Binkert
2008-12-17
Make Alpha pseudo-insts available from SE mode.
Steve Reinhardt
2008-12-07
imported patch aux-fix.patch
Lisa Hsu
2008-12-06
flags: Change naming of functions to be clearer
Nathan Binkert
2008-12-05
This brings M5 closer to modernity - the kernel being advertised is newer so ...
Lisa Hsu
2008-11-15
syscalls: fix latent brk/obreak bug.
Steve Reinhardt
2008-11-14
Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
Nathan Binkert
2008-11-10
pseudo inst: Add rpns (read processor nanoseconds) instruction.
Nathan Binkert
2008-11-10
mem: update stuff for changes to Packet and Request
Nathan Binkert
2008-11-02
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
Lisa Hsu
2008-11-02
Make it so that all thread contexts are registered with the System, even in
Lisa Hsu
2008-11-02
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
Lisa Hsu
2008-10-21
style: Use the correct m5 style for things relating to interrupts.
Nathan Binkert
2008-10-20
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...
Ali Saidi
2008-10-12
Get rid of old RegContext code.
Gabe Black
2008-10-12
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
Gabe Black
[next]