| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-10-01 | arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register | Giacomo Travaglini |
| 2018-05-29 | arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP | Giacomo Travaglini |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2016-12-19 | arm: compute ID_AA64PFR{0,1}_EL1 registers | Curtis Dunham |
| 2016-12-19 | arm: compute ID_PFR{0,1} registers | Curtis Dunham |
| 2016-08-02 | arm: enable EL2 support | Curtis Dunham |
| 2015-10-09 | isa: Add parameter to pick different decoder inside ISA | Rekai Gonzalez Alberquilla |
| 2014-10-16 | arm: Add a model of an ARM PMUv3 | Andreas Sandberg |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2013-01-07 | arm: Make ID registers ISA parameters | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
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index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |