index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
arm
/
ArmISA.py
Age
Commit message (
Expand
)
Author
2019-08-05
arch-arm: Implement ARMv8.1-PAN, Privileged access never
Giacomo Travaglini
2019-07-19
arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disable
Giacomo Travaglini
2019-03-14
arch-arm,cpu: Add initial support for Arm SVE
Giacomo Gabrielli
2019-02-12
python: Don't assume SimObjects live in the global namespace
Andreas Sandberg
2019-01-25
arch-arm: Inital vector rename mode depending on A32/A64
Giacomo Travaglini
2018-10-01
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Giacomo Travaglini
2018-05-29
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
Giacomo Travaglini
2017-07-05
cpu: Added interface for vector reg file
Rekai Gonzalez-Alberquilla
2016-12-19
arm: compute ID_AA64PFR{0,1}_EL1 registers
Curtis Dunham
2016-12-19
arm: compute ID_PFR{0,1} registers
Curtis Dunham
2016-08-02
arm: enable EL2 support
Curtis Dunham
2015-10-09
isa: Add parameter to pick different decoder inside ISA
Rekai Gonzalez Alberquilla
2014-10-16
arm: Add a model of an ARM PMUv3
Andreas Sandberg
2014-01-24
arm: Add support for ARMv8 (AArch64 & AArch32)
ARM gem5 Developers
2013-01-07
arm: Make ID registers ISA parameters
Andreas Sandberg
2013-01-07
arch: Make the ISA class inherit from SimObject
Andreas Sandberg