gem5 - gem5

Age	Commit message (Collapse)	Author
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi

2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi

2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
	SWP and SWPB now throw an undefined instruction exception if SCTLR.SW == 0. This also required the MIDR to be changed slightly so programs can correctly determine that gem5 supports the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were deprecated, but not disabled at CPU startup).
2011-05-13	ARM: Better RealView/Versatile EB platform support.	Chander Sudanthi
	Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively.
2011-05-04	ARM: Add support for loading the a bootloader and configuring parameters for it	Ali Saidi

2010-08-23	ARM: Add system for ARM/Linux and bootstrapping	Ali Saidi

2010-08-23	Loader: Make the load address mask be a parameter of the system rather than ↵	Ali Saidi
	a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0.
2009-11-17	ARM: Boilerplate full-system code.	Ali Saidi
	--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh