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2020-01-22fastmodel: Implement CC reg accessors.Gabe Black
Change-Id: I4d8a7eaa097446b6aa3483880c2a7ed1a2e0d97c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23790 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07fastmodel: Implement the vecPredReg accessor functions.Gabe Black
Change-Id: Iaf6f7d8d1db427bfd486e4bd43f67cc006751873 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23789 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-30fastmodel: Fix compilation errorsChun-Chen TK Hsu
This changes fixes two compilation errors when compiling with FastModels. One is that CurrentMsn should be Iris::CurrentMsn and the other is that currEL() function needs arch/arm/utility.hh header file. Test by compiling GEM5 with FastModels: scons -j64 build/ARM/gem5.opt \ USE_ARM_FASTMODEL=1 \ PVLIB_HOME=... \ MAXCORE_HOME=... \ ARMLMD_LICENSE_FILE=... \ Change-Id: Iabe0a5f25246591f99b57219428b8f87ecd3363c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23924 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.Gabe Black
Now that the IRIS thread context can be specific to ARM, some things which had been pushed to a different level of abstraction can be mvoed back. This will hopefully allow more code sharing in the future when other types of CPUs are supported. Change-Id: Ic3a5f0db53ebe93e18f7507ed71812bce27b6d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23788 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-27fastmodel: Move the ARM IRIS threadcontext into CortexA76.Gabe Black
This specialization will correspond specifically with the CortexA76, instead of specializing the ThreadContext for ARM in general. Some aspects of this class may need to move into the base IRIS thread context class, but I'll leave that for a later change. Change-Id: I9cbe527d36e6fda78601dc39c1963370cfa28b16 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23787 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-27fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.Gabe Black
Fast models are in practice only ARM, so it's not that helpful to have the ARM-ness factored out. It is, however, helpful to have aspects which control how gem5 concepts like registers are mapped to fast model concepts like resources, especially since these mappings may vary from fast model to fast model. For instance, it looks like the CortexA76 does not have predicate vector registers. Rather than make all fast models support or not support those registers, that can be done on a model by model basis. Change-Id: I195da4a2f4d2f8593032d0d63e9fd3d20a240d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23786 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.Gabe Black
The generic thread context checkpointing code can be used which calls into the ThreadContext methods to read the required state. Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
These registers don't have an architectural equivalent, but they may need to be accessed by generic code, for instance the code that checkpoints a thread context. Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
This just calls readVecReg after constructing a RegId. Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
This was hardcoded as 5, but should be determined based on the memory space IDs the fast model returns. What we do now is have a specific override for ARM (perhaps conceptually the A76) which looks for an address space called "Current" which seems to work well. It's possible that the appropriate address space for a different model might have a different number, or even a different name. This may need to be further specialized/parameterized in those cases. Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-23fastmodel: Implement PC based events.Gabe Black
These use the IRIS breakpoint API to stop the models at the appropriate points. There seems to be a slightly wonky interaction between breakpoints and stepping, where if you stop at a breakpoint and then step, you might end up moving forward more than the number of requested instructions. Change-Id: I31f13a120cfc1ad2ec3669ee8befd6d21b328bb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22122 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Tell fast model not to shutdown when time stops.Gabe Black
Change-Id: I000e7809a2c8850eb31e5615caf1d88b537fea8d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22121 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Implement port proxies.Gabe Black
This plumbing is simple and largely copied from other implementations within gem5. This mechanism should be refactored so that the duplication is unnecessary. Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Create a TLB model which uses IRIS to do translations.Gabe Black
Change-Id: I806dc8cdacce57e6ec31d2421b9e6b9733c7da02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22119 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-17fastmodel: Add an address translation mechanism to the ThreadContext.Gabe Black
This will be used by the TLB to do the actual translation. Unfortunately there isn't a great way to tell what translation type to use, so we just go through all of them for now. The ARM subclass might specialize and figure out which address spaces to use based on control register state. Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
Change-Id: I06a7d7db95ec1ce65945c9e09f812f0b69aaa8e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23643 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
The logic that determines which syscall to call was built into the implementation of faults/exceptions or even into the instruction decoder, but that logic can depend on what OS is being used, and sometimes even what version, for example 32bit vs. 64bit. This change pushes that logic up into the Process objects since those already handle a lot of the aspects of emulating the guest OS. Instead, the ISA or fault implementations just notify the rest of the system that a nebulous syscall has happened, and that gets propogated upward until the process does something with it. That's very analogous to how a system call would work on a real machine. When a system call happens, the low level component which detects that should call tc->syscall(&fault), where tc is the relevant thread (or execution) context, and fault is a Fault which can ultimately be set by the system call implementation. The TC implementor (probably a CPU) will then have a chance to do whatever it needs to to handle a system call. Currently only O3 does anything special here. That implementor will end up calling the Process's syscall() method. Once in Process::syscall, the process object will use it's contextual knowledge to determine what system call is being requested. It then calls Process::doSyscall with the right syscall number, where doSyscall centralizes the common mechanism for actually retrieving and calling into the system call implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-03fastmodel: Switch the diagnostic pragmas to GCC from clang.Gabe Black
Clang can handle both, and GCC throws a fit if it sees pragmas for clang. Change-Id: Ie9f2789f45706223b11ed5acdf8b371de6e7ee24 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23321 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03systemc,fastmodel: Use the gem5_scons error and warning functions.Gabe Black
Use them in place of messing with termcap directly. Change-Id: I093efa95e6b6ea7af198dc1395dce05ca6d6575f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23263 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
This header comes from the fast model distribution and so we can't (easily) disable the warning locally. Change-Id: I2c1eee48f8970bb17466f0759f0077a5d45e76af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23123 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is only meanful to GicV2. Test: Boot Android P successfully with the following command: M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel $PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img --kernel-init "/init" --cpu-type fastmodel --machine-type VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0 --mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2 android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5 androidboot.selinux=permissive audit=0 cma=128M" Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-14config: Add fastmodel cluster in fs_bigLITTLE.pyChun-Chen TK Hsu
One can create a system with ARM FastModels CPU and GICv3 with --cpu-type fastmodel --machine-type VExpressFastmodel options. Currently the FastmodelCluster only supports one CPU. Change-Id: I2e985f08f9df01a703e21441c6f9bc1fbae4a222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20901 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-13fastmodel: Implement reading vector registers with readVecReg.Gabe Black
The n other flavors of vector reading functions and all the vector writing functions are not implemented currently. Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-07fastmodel: Plumb the ITB and DTB through the IRIS thread context.Gabe Black
These might be necessary to, for instance, translate virtual addresses. A custom TLB which uses the IRIS API will be written which can be substituted in for the normal ARM TLB. Change-Id: Ic44822db6692ca3a4ca13875b2260b08547a24da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22116 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-06fastmodel: Implement inst count events in the IRIS thread contexts.Gabe Black
These use the IRIS stepping API. Change-Id: Ib45744cb0928fece664187e4df6b25b064b19f0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22115 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Add CortexA76x[234] models.Gabe Black
These use the parameterization added in earlier commits. Change-Id: Id7b99b97894f8fc1f1e5cc34e3e5d32146fed1c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21505 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Enable auto bridging and use it to simplify CortexA76x1.Gabe Black
This lets us avoid having to set up bridges for all the different interrupt signals coming out of the CPU. When we have more cores, like in the x2, x3, and x4 versions of the CPU, we won't have to have a set of bridges for each set of signals, and can connect them all to external ports using array notation, keeping everything simple, concise, and maintainable. Change-Id: I1a5f707073868516e93c106dc17d105409de668a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21504 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31fastmodel: Templatize the xn versions of the CortexA76.Gabe Black
This will make it a lot easier and more succinct to define the x2-x4 versions of that CPU. Change-Id: I951cd3af4419c62892c57968e729fd11c0e4a59e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21503 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30fastmodel: Refactor the CortexA76x1 model for MP support.Gabe Black
This change inverts the relationship between the fast model and gem5 CPUs, and factors out the parts of the CortexA76x1 which are per core vs. per cluster. Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30fastmodel: Helper function to setup FastModels for simulationChun-Chen TK Hsu
This function sets up ARM license, simulation name, and minimum synchronize latency in FastModels. This function should be called once per simulation. Change-Id: Ic3408955aaff9f8b4e2b72d2f2b0da97b41bfc3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22183 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Get rid of the nextInstEventCount method.Gabe Black
This was only used by the KVM CPU, and it has access to all it needs to figure out that value locally without requiring all the ThreadContexts to implement an equivalent function. Change-Id: I17a14ce669db2519edf129db761ebd8dc3bd4129 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22114 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Get rid of the serviceInstCountEvents method.Gabe Black
This was useful when transitioning away from the CPU based comInstEventQueue, but now that objects backing the ThreadContexts have access to the underlying comInstEventQueue and can manipulate it directly, they don't need to do so through a generic interface. Getting rid of this function narrows and simplifies the interface. Change-Id: I202d466d266551675ef6792d38c658d8a8f1cb8b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22113 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Use getCurrentInstCount for totalInsts().Gabe Black
This had been using a custom totalInsts method on the iris ThreadContext, but since that's equivalent to what the totalInsts method does only through a different mechanism, we can drop that and use getCurrentInstCount instead. Change-Id: I058fec13e81f28285281e136635d53a2e849cb47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22112 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Implement getCurrentInstCount.Gabe Black
This uses the step counter the iris API provides. Change-Id: Ic916888fa256d0aa65042d3e6695d9bf4ba32c86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22111 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Switch off of the CPU's comInstEventQueue.Gabe Black
This switches to letting the ThreadContexts use a thread based/local comInstEventQueue instead of falling back to the CPU's array. Because the implementation is no longer shared and it's not given where the comInstEventQueue (or other implementation) should be accessed, the default implementation has been removed. Also, because nobody is using the CPU's array of event queues, those have been removed. Change-Id: I515e6e00a2174067a928c33ef832bc5c840bdf7f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22110 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make the ThreadContext a PCEventScope.Gabe Black
Both the thread and system's PCEventQueue are checked when appropriate. Change-Id: I16c371339c91a37b5641860d974e546a30e23e13 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-23fastmodel: Add string constructors which delegate to const char * ones.Gabe Black
Change-Id: I22d88111409fc477c135b15c8f898adad4f6d4ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21502 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-14fastmodel: Expose all CPU communication ports from the GIC.Gabe Black
The unconnected CPU ports/sockets still need to be connected for TLM to be happy, so this change also adds a terminator module which finds all unbound sockets, creates pair sockets for them to connect to, binds everything together, and implements the target interface with a dummy stub that will complain and crash gem5 if it ever gets called. This will allow us to use the same GIC model to connect an arbitrary number of cores, up to the architected limit of 256. Change-Id: Iaa83fe4f023217dc91a3734b31f764fc4176130e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21500 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-09fastmodel: Export GICV3Comms directly.Gabe Black
This lets us avoid having to have two levels of bridging and twice as many ports on both the CPU and GIC side. The direct communication ports can be instantiated and connected using array syntax, where the bridges require instantiating each bridge individually and wiring them up one at a time with a lot of boilerplate/duplicate code. Change-Id: I815ee47bcd19994e46a5220e0c23e89c497d7aa5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21050 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-07fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.Gabe Black
This makes it easier to wire up CPUs to the interrupt controller, and makes things more modular. Change-Id: I8d3ab26e4bb588b8efb198ed145d0f58b7ee04cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21049 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
This was to support port proxies and getInstPort and getDataPort. With some recent upstream changes, getInstPort and getDataPort are only used for CPU switching which we can't support (TLM ports are bound permanently), and with the sendFunctional delegate for port proxies, we don't need to have a traditional gem5 port lying around. This gets rid of the "mem" port and all its plumbing. Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
The iris CPU model doesn't necessarily know the best way to send functional packets (what port? what type is that port?), but only has a generic sc_module pointer to the EVS and so can't call specialized methods on it. There also isn't any common base class for EVSes to cast into in a generic way. This attribute mechanism lets the EVS set up its own sendFunctional implementation however it needs to using facilities that are built into generic sc_objects. Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
This attribute is to let the fast model EVS CPU find and talk to the gem5 CPU in case it needs a pointer to one of its ThreadContexts for instance. Also move the code that finds the clock period attribute/event to the constructor. gem5 guarantees that the EVS is constructed before its pointer is passed to the iris CPU wrapper, and so the EVS will have had a chance to install those controls if it's going to. Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
These signals come from the exported virtual subsystem and could signal interrupts, etc. The new SignalReceiver class makes it easier to watch those signals and perform some behavior when they change without having to bring along a lot of systemc baggage. Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
This change pulls out the SPI and PPI command structures and replaces them with a custom protocol which can deliver a SPI or PPI without having to bundle their parameters into a structure. Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
Fast Models are models written by ARM which emulate different components of a computer system. They can be combined into small subsystems and then exported as systemc modules. To enable this code, you'll need to set USE_ARM_FASTMODEL variable to true. This CL does not include the fast models themselves, or a license to use them or the associated tools. To build these fast models, you'll need to set some scons variables. These variables should be set as described in the fast model distribution. * PVLIB_HOME * MAXCORE_HOME * ARMLMD_LICENSE_FILE Some minor patches to source filesdistributed with the fast model code may be necessary since their use of systemc is not necessarily 100% standards compliant. Change-Id: Id53814b95d8aa320da4d4f2159be0736fc12eb73 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20799 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-26 23:47:23 +0000