gem5 - gem5

Age	Commit message (Collapse)	Author
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP ↵	Gabe Black
	access is disabled.
2010-08-23	ARM: Make sure that software prefetch instructions can't change the state of ↵	Gene Wu
	the TLB
2010-08-23	ARM: adding genMachineCheckFault() stub for ARM that doesn't panic	Min Kyu Jeong

2010-08-23	ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵	Gene Wu
	ARMv7
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi

2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi

2010-06-02	ARM: Implement and update the DFSR and IFSR registers on faults.	Gabe Black

2010-06-02	ARM: Trigger system calls from the SupervisorCall invoke method.	Gabe Black
	This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic.
2010-06-02	ARM: Rework how unrecognized/unimplemented instructions are handled.	Gabe Black
	Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic.
2009-11-10	ARM: Implement fault classes.	Gabe Black
	Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-04-05	arm: add ARM support to M5	Stephen Hines