| Age | Commit message (Expand) | Author |
|---|
| 2018-11-28 | arch-arm: Add missing template declaration | Nikos Nikoleris |
| 2018-11-07 | arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 | Giacomo Travaglini |
| 2018-06-06 | arch-arm: Adjust breakpoint EC depending on source state | Andreas Sandberg |
| 2018-03-08 | arch-arm: Fix FSC generation in AbortFault | Giacomo Travaglini |
| 2018-03-08 | arch-arm: Introduce update method in ArmFault class | Giacomo Travaglini |
| 2018-03-08 | arch-arm: Fix PCAlignmentFault routing to Hypervisor | Giacomo Travaglini |
| 2018-02-13 | sim: Make Stats truly non-copy-constructible | Rekai Gonzalez-Alberquilla |
| 2018-02-08 | arch-arm: Fixed error in choosing vector offset | Chuan Zhu |
| 2018-02-08 | arch-arm: Handle route to EL2 in Supervisor Trap | Chuan Zhu |
| 2017-12-21 | arch-arm: Hyp routed undef fault need to change its syndrome | Giacomo Travaglini |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-22 | arch-arm: Add support for the brk instruction | Andreas Sandberg |
| 2017-11-15 | arch-arm: Removing FlushPipe fault, using SquashAfter | Giacomo Travaglini |
| 2017-08-30 | arch-arm: Add missing override keywords in fault.hh | Andreas Sandberg |
| 2017-05-19 | base, sim, arch: Fix clang 5.0 warnings | Andreas Sandberg |
| 2017-04-03 | arm: fix template instantiation warning in clang | Matteo Andreozzi |
| 2016-08-02 | arm: Add AArch64 hypervisor call instruction 'hvc' | Dylan Johnson |
| 2016-01-11 | scons: Enable -Wextra by default | Andreas Hansson |
| 2014-11-14 | arm: Fixes based on UBSan and static analysis | Andreas Hansson |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-04-17 | arm: Make sure UndefinedInstructions are properly initialized | Ali Saidi |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2011-11-02 | SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. | Gabe Black |
| 2011-09-27 | Faults: Replace calls to genMachineCheckFault with M5PanicFault. | Gabe Black |
| 2011-09-13 | LSQ: Only trigger a memory violation with a load/load if the value changes. | Ali Saidi |
| 2011-08-19 | Fix bugs due to interaction between SEV instructions and O3 pipeline | Geoffrey Blake |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-04-04 | ARM: Fix table walk going on while ASID changes error | Ali Saidi |
| 2011-01-18 | O3: Fixes the way prefetches are handled inside the iew unit. | Matt Horsnell |
| 2011-01-03 | Make commenting on close namespace brackets consistent. | Steve Reinhardt |
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black |
| 2010-08-25 | ARM: Adding a bogus fault that does nothing. | Min Kyu Jeong |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP access... | Gabe Black |
| 2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ... | Gene Wu |
| 2010-08-23 | ARM: adding genMachineCheckFault() stub for ARM that doesn't panic | Min Kyu Jeong |
| 2010-08-23 | ARM: DFSR status value for sync external data abort is expected to be 0x8 in ... | Gene Wu |
| 2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi |
| 2010-06-02 | ARM: Implement ARM CPU interrupts | Ali Saidi |
| 2010-06-02 | ARM: Implement and update the DFSR and IFSR registers on faults. | Gabe Black |
| 2010-06-02 | ARM: Trigger system calls from the SupervisorCall invoke method. | Gabe Black |
| 2010-06-02 | ARM: Rework how unrecognized/unimplemented instructions are handled. | Gabe Black |
| 2009-11-10 | ARM: Implement fault classes. | Gabe Black |
| 2009-04-05 | arm: add ARM support to M5 | Stephen Hines |
