gem5 - gem5

Age	Commit message (Expand)	Author
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	ARM: Fix table walk going on while ASID changes error	Ali Saidi
2011-01-18	O3: Fixes the way prefetches are handled inside the iew unit.	Matt Horsnell
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-08-25	ARM: Adding a bogus fault that does nothing.	Min Kyu Jeong
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP access...	Gabe Black
2010-08-23	ARM: Make sure that software prefetch instructions can't change the state of ...	Gene Wu
2010-08-23	ARM: adding genMachineCheckFault() stub for ARM that doesn't panic	Min Kyu Jeong
2010-08-23	ARM: DFSR status value for sync external data abort is expected to be 0x8 in ...	Gene Wu
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi
2010-06-02	ARM: Implement and update the DFSR and IFSR registers on faults.	Gabe Black
2010-06-02	ARM: Trigger system calls from the SupervisorCall invoke method.	Gabe Black
2010-06-02	ARM: Rework how unrecognized/unimplemented instructions are handled.	Gabe Black
2009-11-10	ARM: Implement fault classes.	Gabe Black
2009-04-05	arm: add ARM support to M5	Stephen Hines