gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-23	arch-arm: Remove SWP and SWPB instructions	Giacomo Travaglini
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2010-06-02	ARM: Make some of the trace code more compact	Ali Saidi
2010-06-02	ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.	Gabe Black
2010-06-02	ARM: Implement the SRS instruction.	Gabe Black
2010-06-02	ARM: Add a base class for SRS.	Gabe Black
2010-06-02	ARM: Add a base class for the RFE instruction.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Implement the swp and swpb instructions.	Gabe Black
2010-06-02	ARM: Remove the special naming for the new memory instructions.	Gabe Black
2010-06-02	ARM: Eliminate the old memory formats which are no longer used.	Gabe Black
2010-06-02	ARM: Implement a new set of base classes for non macro memory instructions.	Gabe Black
2009-07-08	ARM: Improve memory instruction disassembly.	Gabe Black
2009-06-27	ARM: Write a function for printing mnemonics and predicates.	Gabe Black
2009-06-21	ARM: Simplify the ISA desc by pulling some classes out of it.	Gabe Black