| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-01-23 | arch-arm: Remove SWP and SWPB instructions | Giacomo Travaglini | |
| The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> | |||
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu | |
| Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 | |||
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter | |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers | |
| Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black | |||
| 2010-06-02 | ARM: Make some of the trace code more compact | Ali Saidi | |
| 2010-06-02 | ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file. | Gabe Black | |
| 2010-06-02 | ARM: Implement the SRS instruction. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for SRS. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for the RFE instruction. | Gabe Black | |
| 2010-06-02 | ARM: Explicitly keep track of the second destination for double loads/stores. | Gabe Black | |
| 2010-06-02 | ARM: Implement the swp and swpb instructions. | Gabe Black | |
| 2010-06-02 | ARM: Remove the special naming for the new memory instructions. | Gabe Black | |
| These are the only memory instructions now. | |||
| 2010-06-02 | ARM: Eliminate the old memory formats which are no longer used. | Gabe Black | |
| 2010-06-02 | ARM: Implement a new set of base classes for non macro memory instructions. | Gabe Black | |
| 2009-07-08 | ARM: Improve memory instruction disassembly. | Gabe Black | |
| 2009-06-27 | ARM: Write a function for printing mnemonics and predicates. | Gabe Black | |
| 2009-06-21 | ARM: Simplify the ISA desc by pulling some classes out of it. | Gabe Black | |
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