gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-23	arch-arm: Remove SWP and SWPB instructions	Giacomo Travaglini
2018-03-26	arch: Fix all override related warnings.	Gabe Black
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
2011-01-18	ARM: fix mismatched new/delete.	Ali Saidi
2010-11-15	ARM: Use the correct delete operator for RFE	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
2010-06-02	ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.	Gabe Black
2010-06-02	ARM: Add a base class for SRS.	Gabe Black
2010-06-02	ARM: Implement the strex instructions.	Gabe Black
2010-06-02	ARM: Add a base class for the RFE instruction.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Implement the swp and swpb instructions.	Gabe Black
2010-06-02	ARM: Remove the special naming for the new memory instructions.	Gabe Black
2010-06-02	ARM: Eliminate the old memory formats which are no longer used.	Gabe Black
2010-06-02	ARM: Implement a new set of base classes for non macro memory instructions.	Gabe Black
2009-07-08	ARM: Improve memory instruction disassembly.	Gabe Black
2009-07-08	ARM: Get rid of the MemAcc and EAComp static insts.	Gabe Black
2009-07-08	ARM: Add an AddrMode2 format for memory instructions that use address mode 2.	Gabe Black
2009-07-08	ARM: Add an AddrMode3 format for memory instructions that use address mode 3.	Gabe Black
2009-06-21	ARM: Simplify the ISA desc by pulling some classes out of it.	Gabe Black