| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter | |
| 2014-09-27 | arm: Fixed undefined behaviours identified by gcc | Andreas Hansson | |
| This patch fixes the runtime errors highlighted by the undefined behaviour sanitizer. In the end there were two issues. First, when rotating an immediate, we ended up shifting an uint32_t by 32 in some cases. This case is fixed by checking for a rotation by 0 positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex as an IntRegIndex. This issue is resolved by introducing a MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types. With these fixes there are no runtime errors identified for the full ARM regressions. | |||
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers | |
| Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black | |||
| 2013-10-15 | cpu: rename *_DepTag constants to *_Reg_Base | Steve Reinhardt | |
| Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g; | |||
| 2013-10-15 | cpu: clean up architectural register classification | Steve Reinhardt | |
| Move from a poorly documented scheme where the mapping of unified architectural register indices to register classes is hardcoded all over to one where there's an enum for the register classes and a function that encapsulates the mapping. | |||
| 2010-06-02 | ARM: Get rid of the binary dumping function in utility.hh. | Gabe Black | |
| 2010-06-02 | ARM: Make undefined instructions obey predication. | Gabe Black | |
| 2010-06-02 | ARM: Add a new RegImmOp base class. | Gabe Black | |
| 2010-06-02 | ARM: Add a RegRegImmOp base class. | Gabe Black | |
| 2010-06-02 | ARM: Make a base class for instructions that use only an immediate. | Gabe Black | |
| 2010-06-02 | ARM: Rename the RevOp base class to something more generic. | Gabe Black | |
| 2010-06-02 | ARM: Add a register, immediate, immediate to register base for [su]bfx. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class to support usada8. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for the sel instruction. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for extend and add instructions. | Gabe Black | |
| 2010-06-02 | ARM: Generalize the saturation instruction bases for use in other instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement base classes for the saturation instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add base classes suitable for the REV* instructions. | Gabe Black | |
| 2010-06-02 | ARM: Define versions of MSR and MRS outside the decoder. | Gabe Black | |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |