gem5 - gem5

Age	Commit message (Expand)	Author
2017-12-05	arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions	Nikos Nikoleris
2017-11-21	arch-arm: Fix MCR/MRC disassemble	Giacomo Travaglini
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2014-09-27	arm: Fixed undefined behaviours identified by gcc	Andreas Hansson
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-10-15	cpu: clean up architectural register classification	Steve Reinhardt
2010-06-02	ARM: Get rid of the binary dumping function in utility.hh.	Gabe Black
2010-06-02	ARM: Make undefined instructions obey predication.	Gabe Black
2010-06-02	ARM: Add a new RegImmOp base class.	Gabe Black
2010-06-02	ARM: Add a RegRegImmOp base class.	Gabe Black
2010-06-02	ARM: Make a base class for instructions that use only an immediate.	Gabe Black
2010-06-02	ARM: Rename the RevOp base class to something more generic.	Gabe Black
2010-06-02	ARM: Add a register, immediate, immediate to register base for [su]bfx.	Gabe Black
2010-06-02	ARM: Add a base class to support usada8.	Gabe Black
2010-06-02	ARM: Add a base class for the sel instruction.	Gabe Black
2010-06-02	ARM: Add a base class for extend and add instructions.	Gabe Black
2010-06-02	ARM: Generalize the saturation instruction bases for use in other instructions.	Gabe Black
2010-06-02	ARM: Implement base classes for the saturation instructions.	Gabe Black
2010-06-02	ARM: Add base classes suitable for the REV* instructions.	Gabe Black
2010-06-02	ARM: Define versions of MSR and MRS outside the decoder.	Gabe Black