gem5 - gem5

Age	Commit message (Expand)	Author
2017-11-07	alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.	Gabe Black
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-09-27	arm: Fixed undefined behaviours identified by gcc	Andreas Hansson
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-25	ARM: Implement all ARM SIMD instructions.	Gabe Black
2010-06-02	ARM: Decode to specialized conditional/unconditional versions of instructions.	Gabe Black
2010-06-02	ARM: Add a function to decode VFP modified immediate constants.	Gabe Black
2010-06-02	ARM: Add a function to decode SIMD modified immediate constants.	Gabe Black
2010-06-02	ARM: Get rid of obsoleted predicated inst formats, etc.	Gabe Black
2010-06-02	ARM: Implement disassembly for the new data processing classes.	Gabe Black
2010-06-02	ARM: Move the modified_imm function from all ARM instructions to just data pr...	Gabe Black
2010-06-02	ARM: Add new base classes for data processing instructions.	Gabe Black
2010-06-02	ARM: Add a base class for 32 bit thumb data processing immediate instructions.	Gabe Black
2010-06-02	ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.	Gabe Black
2009-07-08	ARM: Tune up predicated instruction decoding.	Gabe Black
2009-06-27	ARM: Show more information when disassembling data processing intstructions.	Gabe Black
2009-06-21	ARM: Simplify the ISA desc by pulling some classes out of it.	Gabe Black