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2011-04-15includes: sort all includesNathan Binkert
2011-04-04ARM: Remove debugging warn that was accidently left in.Ali Saidi
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path.
2011-01-18ARM: fix mismatched new/delete.Ali Saidi
2010-11-15ARM: Use the correct delete operator for RFEAli Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-01ARM: Clean up use of TBit and JBit.Ali Saidi
Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code.
2010-08-25ARM: Use fewer micro-ops for register update loads if possible.Gene WU
Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP ↵Gabe Black
access is disabled.
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2010-06-02ARM: Add a comment to vfp.cc that explains the asm statements.Gabe Black
2010-06-02ARM: Add comments to the classes in macromem.hh.Gabe Black
2010-06-02ARM: Move code from vfp.hh to vfp.cc.Gabe Black
2010-06-02ARM: Make some of the trace code more compactAli Saidi
2010-06-02ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.Gabe Black
2010-06-02ARM: Get rid of the binary dumping function in utility.hh.Gabe Black
2010-06-02ARM: Get rid of the empty branch.cc.Gabe Black
2010-06-02ARM: Mark some ARM static inst functions as inline.Gabe Black
2010-06-02ARM: Decode to specialized conditional/unconditional versions of instructions.Gabe Black
This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them.
2010-06-02ARM: Make undefined instructions obey predication.Gabe Black
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Implement conversion to/from half precision.Gabe Black
2010-06-02ARM: Clean up VFPGabe Black
2010-06-02ARM: Clean up the implementation of the VFP instructions.Gabe Black
2010-06-02ARM: Fix double precision load/store multiple decrement.Gabe Black
When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.
2010-06-02ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.Gabe Black
2010-06-02ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's ↵Gabe Black
after.
2010-06-02ARM: Implement flush to zero for destinations as well.Gabe Black
2010-06-02ARM: Fix up nans to match ARM's expected behavior.Gabe Black
2010-06-02ARM: Implement flush to zero mode for VFP, and clean up some corner cases.Gabe Black
2010-06-02ARM: Add barriers that make sure FP operations happen where they're supposed to.Gabe Black
2010-06-02ARM: Implement the floating/fixed point VCVT instructions.Gabe Black
2010-06-02ARM: Add code to extract and record VFP exceptions.Gabe Black
2010-06-02ARM: Add support for VFP vector mode.Gabe Black
2010-06-02ARM: Introduce new VFP base classes that are optionally microops.Gabe Black
2010-06-02ARM: Implement the VFP version of vmul.Gabe Black
2010-06-02ARM: Make sure macroops aren't interrupted midinstruction.Gabe Black
Do this by setting the delayed commit flag for all but the last microop.
2010-06-02ARM: Fix the implementation of the VFP ldm and stm macroops.Gabe Black
There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02ARM: Add a new RegImmOp base class.Gabe Black
2010-06-02ARM: Add a RegRegImmOp base class.Gabe Black
2010-06-02ARM: Widen the immediate fields in the misc instruction classes.Gabe Black
2010-06-02ARM: Add a function to decode VFP modified immediate constants.Gabe Black
2010-06-02ARM: Add a function to decode SIMD modified immediate constants.Gabe Black
2010-06-02ARM: Ignore writing a bad mode to CPSR with MSR.Gabe Black
2010-06-02ARM: Implement the SRS instruction.Gabe Black