| Age | Commit message (Expand) | Author |
|---|
| 2018-10-26 | arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL | Giacomo Travaglini |
| 2018-10-26 | arch-arm: Refactor AArch64 MSR/MRS trapping | Giacomo Travaglini |
| 2018-10-09 | arch-arm: AArch32 Crypto AES | Matt Horsnell |
| 2018-10-09 | arch-arm: AArch32 Crypto SHA | Matt Horsnell |
| 2018-10-02 | arch-arm: Add FP16 support introduced by Armv8.2-A | Edmund Grimley Evans |
| 2018-10-02 | arch-arm: Add FP16 support and other primitives to fplib | Edmund Grimley Evans |
| 2018-06-22 | arch-arm: AArch32 execution triggering AArch64 SW Break | Giacomo Travaglini |
| 2018-06-22 | arch-arm: BadMode checking if corresponding EL is implemented | Giacomo Travaglini |
| 2018-06-14 | arch-arm: Add Illegal Execution flag to PCState | Giacomo Travaglini |
| 2018-04-19 | arch-arm: Fix Unknown Instruction disassemble | Giacomo Travaglini |
| 2018-04-06 | arch-arm: Fix AArch32 branch instructions disassemble | Giacomo Travaglini |
| 2018-04-06 | arch-arm: Correct mcrr,mrrc disassemble | Giacomo Travaglini |
| 2018-03-26 | arch: Fix all override related warnings. | Gabe Black |
| 2018-03-26 | arch: Add a virtual asBytes function to the StaticInst class. | Gabe Black |
| 2018-03-15 | arm: Fix implicit-fallthrough warnings when building with gcc-7+ | Siddhesh Poyarekar |
| 2018-02-20 | arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly | Giacomo Travaglini |
| 2018-02-16 | arch-arm: IMPLEMENTATION DEFINED register | Giacomo Travaglini |
| 2018-02-16 | arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64 | Chuan Zhu |
| 2018-02-08 | arch-arm: Don't change PSTATE in Illegal Exception return | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix printing of the data cache maintenance instructions | Nikos Nikoleris |
| 2018-02-07 | arch-arm: Change function name for banked miscregs | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix AArch32 SETEND Instruction | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Correct Illegal Exception Return detection | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Fixed WFE/WFI trapping behaviour | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Fix StaticInst encoding() method | Giacomo Travaglini |
| 2017-12-19 | arch-arm: Instruction size methods in StaticInst class | Giacomo Travaglini |
| 2017-12-05 | arm: Add support for the dc {civac, cvac, cvau, ivac} instr | Nikos Nikoleris |
| 2017-12-05 | arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions | Nikos Nikoleris |
| 2017-11-21 | arch-arm: Fix MCR/MRC disassemble | Giacomo Travaglini |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Writes to DCCMVAC shouldn't flush pipeline | Giacomo Travaglini |
| 2017-11-15 | arch-arm: Removing FlushPipe fault, using SquashAfter | Giacomo Travaglini |
| 2017-11-13 | arch-arm: Interface for the ArmStaticInst intWidth field | Giacomo Travaglini |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-05-19 | base, sim, arch: Fix clang 5.0 warnings | Andreas Sandberg |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-10-13 | isa,arm: Add missing AArch32 FP instructions | Mitch Hayenga |
| 2016-08-02 | arm: change instruction classes to catch hyp traps | Dylan Johnson |
| 2016-06-02 | arm: Rewrite ERET to behave according to the ARMv8 ARM | Andreas Sandberg |
| 2016-06-02 | arm: Correctly check FP/SIMD access permission in aarch32 | Andreas Sandberg |
| 2016-03-16 | arm: Fix disasm printing | Nathanael Premillieu |
| 2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
| 2015-11-22 | arm: Fix fplib 128-bit shift operators | Nathanael Premillieu |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-02-16 | arm: Merge ISA files with pseudo instructions | Andreas Sandberg |
